CYP15G0401DXB-BGXC View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
MFG CO.
'CYP15G0401DXB-BGXC' PDF : 53 Pages View PDF
CYP15G0401DXB
CYV15G0401DXB
CYW15G0401DXB
CYP(V)(W)15G0401DXB HOTLink II Transmitter Switching Waveforms
Transmit Interface Write Timing
TXCKSEL ≠ LOW
tTXCLKH
tTXCLK
tTXCLKL
TXCLKx
TXDx[7:0],
TXCTx[1:0],
TXOPx,
SCSEL
tTXDS
Transmit Interface Write Timing
TXCKSEL = LOW
TXRATE = LOW
tREFH
tREFCLK
tREFL
tTXDH
REFCLK
TXDx[7:0],
TXCTx[1:0],
TXOPx,
SCSEL
Transmit Interface
Write Timing
TXCKSEL = LOW
TXRATE = HIGH
REFCLK
TXDx[7:0],
TXCTx[1:0],
TXOPx,
SCSEL
Transmit Interface
TXCLKO Timing
TXCKSEL = LOW
TXRATE = HIGH
tTREFDS
Note 44
tREFH
tREFCLK
Note 44
tTREFDS
tTREFDH
tREFL
tTREFDS
tTREFDH
tREFH
tREFCLK
tTREFDH
tREFL
REFCLK
Note 46
TXCLKO
tTXCLKO
tTXCLKOD+
tTXCLKOD–
Note 45
Notes:
44. When REFCLK is configured for half-rate operation (TXRATE = HIGH) and data is captured using REFCLK instead of a TXCLKx clock (TXCKSEL = LOW), data
is captured using both the rising and falling edges of REFCLK.
45. The TXCLKO output is at twice the rate of REFCLK when TXRATE = HIGH and same rate as REFCLK when TXRATE = LOW. TXCLKO does not follow the
duty cycle of REFCLK.
46. The rising edge of TXCLKO output has no direct phase relationship to the REFCLK input.
Document #: 38-02002 Rev. *L
Page 39 of 53
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