DM9008C View Datasheet(PDF) - Davicom Semiconductor, Inc.
Part Name
Description
MFG CO.
'DM9008C' PDF : 52 Pages View PDF
5.8
5.7
5.6
5.5
5.4-5.0
TX_FDX
TX_HDX
10_FDX
10_HDX
Selector
DM9008C
Ethernet Controller with General Processor Interface
(The DM9008C only support 100M Fiber mode).
0, RO 100BASE-TX Full Duplex Support
1 = 100BASE-TX full duplex is supported by the link partner
0 = 100BASE-TX full duplex is not supported by the link partner
(The DM9008C only support 100M Fiber mode).
0, RO 100BASE-TX Support
1 = 100BASE-TX half duplex is supported by the link partner
0 = 100BASE-TX half duplex is not supported by the link partner
(The DM9008C only support 100M Fiber mode).
0, RO 10BASE-T Full Duplex Support
1 = 10BASE-T full duplex is supported by the link partner
0 = 10BASE-T full duplex is not supported by the link partner
0, RO 10BASE-T Support
1 = 10BASE-T half duplex is supported by the link partner
0 = 10BASE-T half duplex is not supported by the link partner
<00000>, RO Protocol Selection Bits
Link partner’s binary encoded protocol selector
8.7 Auto-negotiation Expansion Register (ANER)- 06
Bit
Bit Name
Default
Description
6.15-6.5 Reserved
0, RO
Reserved
Read as 0, ignore on write
6.4
PDF
0, RO/LH Local Device Parallel Detection Fault
PDF = 1: A fault detected via parallel detection function.
PDF = 0: No fault detected via parallel detection function
6.3 LP_NP_ABLE
0, RO Link Partner Next Page Able
LP_NP_ABLE = 1: Link partner, next page available
LP_NP_ABLE = 0: Link partner, no next page
6.2
NP_ABLE
0,RO/P Local Device Next Page Able
NP_ABLE = 1: DM9008C, next page available
NP_ABLE = 0: DM9008C, no next page
DM9008C does not support this function, so this bit is always 0
6.1
PAGE_RX
0, RO/LH New Page Received
A new link code word page received. This bit will be automatically
cleared when the register (register 6) is read by management
6.0 LP_AN_ABLE
0, RO Link Partner Auto-negotiation Able
A “1” in this bit indicates that the link partner supports
Auto-negotiation
8.8 DAVICOM Specified Configuration Register (DSCR) - 16
Bit
Bit Name
Default
Description
16.15
BP_4B5B
0,RW Bypass 4B5B Encoding and 5B4B Decoding
1 = 4B5B encoder and 5B4B decoder function bypassed
0 = Normal 4B5B and 5B4B operation
16.14
BP_SCR
0, RW Bypass Scrambler/Descrambler Function
1 = Scrambler and descrambler function bypassed
0 = Normal scrambler and descrambler operation
16.13 BP_ALIGN
0, RW Bypass Symbol Alignment Function
1 = Receive functions (descrambler, symbol alignment and symbol
decoding functions) bypassed. Transmit functions (symbol encoder
Preliminary
32
Version: DM9008C-13-DS-P01
January 15, 2008
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