DM9010B View Datasheet(PDF) - Davicom Semiconductor, Inc.
Part Name
Description
MFG CO.
DM9010B
Davicom Semiconductor, Inc.
'DM9010B' PDF : 62 Pages View PDF
14
6,7,8,9,10,
11,12,13,
89,88,87,
86,85,84,
83,82
93,94,95,
96,97,98
RST
SD0~15
SA4~9
92
CMD
91
IO16
100
INT
56,53,52,
51,50,49,
47,46,45,
44,43,41,
40,39,38
37
57
SD16~31 (in
double word
mode)
IO32 (in double
word mode)
DM9010B
Single Chip Ethernet Controller with General Processor Interface
I Hardware Reset Command, active high to reset the DM9010B
I/O,PD Processor Data Bus bit 0~15
I,PD Address Bus 4~9
These pins are used to select the DM9010B.
When SA9 and SA8 are in high states, and SA7 and AEN are in low
states, and SA6~4 are matched with strap pins TXD2~0, the DM9010B is
selected.
I,PD Command Type
When high, the access of this command cycle is DATA port
When low, the access of this command cycle is INDEX port
O Word Command Indication
When the access of internal memory is word or Dword width, this pin will
be asserted
This pin is low active at default; its polarity can be modified by EEPROM
setting. See the EEPROM content description for detail
O,PD Interrupt Request
This pin is high active at default, its polarity can be modified by EEPROM
setting or strap pin MDC. See the EEPROM content description for detail
I/O,PD Processor Data Bus bit 16~31
These pins are used as data bus bits 16~31 when the DM9010B is set to
double word mode (the straps pin EEDO is pulled high and WAKE is not
pull-high)
O,PD
Double Word Command Indication
This pins is used as the double word command indication when the
DM9010B is set to double data word mode, and this pin will be asserted
when the access of internal memory is double word width
This pin is low active at default; its polarity can be modified by EEPROM
setting. See the EEPROM content description for detail
When the IO32 pin is pulled high, the INT pin is low active; otherwise the INT pin
is high active
Preliminary
12
Version: DM9010B--DS-P01
September 5, 2007
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