DS28E05
1-Wire EEPROM
Resume Command [A5h]
To maximize the data throughput in a multidrop environ
ment, the Resume command is available. This command
checks the status of the RC bit and, if it is set, directly
transfers control to the memory functions, similar to a
Skip ROM command. The only way to set the RC bit is
through successfully executing the Match ROM or Search
ROM command. Once the RC bit is set, the device can
repeatedly be accessed through the Resume command.
Accessing another device on the bus clears the RC bit,
preventing two or more devices from simultaneously
responding to the Resume command.
1-Wire Signaling
The DS28E05 requires strict protocols to ensure data
integrity. The protocol consists of four types of signaling
on one line: reset sequence with reset pulse and presence
pulse, write-zero, write-one, and read-data. Except for the
presence pulse, the bus master initiates all falling edges.
The DS28E05 communicates at overdrive speed only.
To get from idle to active, the voltage on the 1-Wire line
needs to fall from VPUP below the threshold VTL. To get
from active to idle, the voltage needs to rise from VIL(MAX)
past the threshold VTH. The time it takes for the voltage
to make this rise is seen in Figure 9 as ε, and its duration
depends on the pullup resistor (RPUP) used and the
capacitance of the 1-Wire network attached. The voltage
VIL(MAX) is relevant for the DS28E05 when determining a
logical level, not triggering any events.
Figure 9 shows the initialization sequence required to
begin any communication with the DS28E05. A reset
pulse followed by a presence pulse indicates that the
DS28E05 is ready to receive data, given the correct ROM
and memory function command. If the bus master uses
slew-rate control on the falling edge, it must pull down the
line for tRSTL + tF to compensate for the edge.
After the bus master has released the line it goes into
receive mode. Now the 1-Wire bus is pulled to VPUP through
the pullup resistor. When the threshold VTH is crossed, the
DS28E05 waits and then transmits a presence pulse by
pulling the line low. To detect a presence pulse, the master
must test the logical state of the 1-Wire line at tMSP.
Read-/Write-Time Slots
Data communication with the DS28E05 takes place in
time slots that carry a single bit each. Write time slots
transport data from bus master to slave. Read time slots
transfer data from slave to master. Figure 10 illustrates
the definitions of the write- and read-time slots.
All communication begins with the master pulling the data
line low. As the voltage on the 1-Wire line falls below
the threshold VTL, the DS28E05 starts its internal timing
generator that determines when the data line is sampled
during a write time slot and how long data is valid during
a read time slot.
Master-to-Slave
For a write-one time slot, the voltage on the data line
must have crossed the VTH threshold before the write-
one low time tW1L(MAX) is expired. For a write-zero time
slot, the voltage on the data line must stay below the
VTH threshold until the write-zero low time tW0L(MIN) is
expired. For the most reliable communication, the voltage
on the data line should not exceed VIL(MAX) during the
entire tW0L or tW1L window. After the VTH threshold has
been crossed, the DS28E05 needs a recovery time tREC
before it is ready for the next time slot.
VPUP
VIHMASTER
VTH
VTL
VIL(MAX)
0V
MASTER Tx "RESET PULSE"
tRSTL
tF
RESISTOR
MASTER Rx "PRESENCE PULSE"
ε
tMSP
MASTER
tRSTH
tREC
DS28E05
Figure 9. Initialization Procedure: Reset and Presence Pulse
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