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DS28E05 View Datasheet(PDF) - Maxim Integrated

Part Name
Description
MFG CO.
DS28E05
MaximIC
Maxim Integrated MaximIC
'DS28E05' PDF : 17 Pages View PDF
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DS28E05
1-Wire EEPROM
The sum of tRL + δ (rise time) on one side and the internal
timing generator of the DS28E05 on the other side define
the master sampling window (tMSR(MIN) to tMSR(MAX)), in
which the master must perform a read from the data line.
For the most reliable communication, tRL should be as
short as permissible, and the master should read close to
but no later than tMSR(MAX). After reading from the data
line, the master must wait until tSLOT is expired. This
guarantees sufficient recovery time tREC for the DS28E05
to get ready for the next time slot. Note that tREC specified
herein applies only to a single DS28E05 attached to a
1-Wire line. For multidevice configurations, tREC must be
extended to accommodate the additional 1-Wire device
input capacitance.
Improved Network Behavior
(Switchpoint Hysteresis)
In a 1-Wire environment, line termination is possible only
during transients controlled by the bus master (1-Wire
driver). 1-Wire networks, therefore, are susceptible to
noise of various origins. Depending on the physical size
and topology of the network, reflections from end points
and branch points can add up or cancel each other to
some extent. Such reflections are visible as glitches or
VPUP
VTH
VHY
VTL
0V
Figure 11. Noise Suppression Scheme
ringing on the 1-Wire communication line. Noise coupled
onto the 1-Wire line from external sources can also result
in signal glitching. A glitch during the rising edge of a time
slot can cause a slave device to lose synchronization
with the master and, consequently, result in a Search
ROM command coming to a dead end or cause a device-
specific function command to abort. The DS28E05 uses a
1-Wire front-end with built-in hysteresis at the low-to-high
switching threshold VTH. If a negative glitch crosses VTH
but does not go below VTL, it is not recognized (Figure 11).
1-Wire Communication Examples
See Table 5 and Table 6 for the 1-Wire communication
legend and data direction codes.
Table 5. 1-Wire Communication Legend
SYMBOL
RST
PD
Select
PB
CS
Release
WM
RM
<n bytes>
<data to EOP>
Data
FF loop
DESCRIPTION
1-Wire reset pulse generated by master
1-Wire presence detect pulse generated by slave
Command and data to satisfy the ROM function protocol
Parameter byte
Command Success indicator
FFh byte sent by the master to start a write activity in the slave
Command “Write Memory”
Command “Read Memory”
Transfer of n bytes
Transfer of as many bytes as are needed to reach the end of the page
Transfer of 2 bytes segment data
Indefinite loop where the bus master reads FFh bytes
Table 6. Data Direction Codes
Master-to-Slave Slave-to-Master Master waits (1-Wire idle high)
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