DSM2180F3 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
DSM2180F3
STMicroelectronics
'DSM2180F3' PDF : 63 Pages View PDF
DSM2180F3
Table 32. Write Timing
Symbol
Parameter
Conditions
-90
Unit
Min.
Max.
tAVWL Address Valid to Leading Edge of WR
(Note 1)
0
ns
tSLWL
CS Valid to Leading Edge of WR
0
ns
tDVWH WR Data Setup Time
35
ns
tWHDX WR Data Hold Time
4
ns
tWLWH WR Pulse Width
35
ns
tWHAX1 Trailing Edge of WR to Address Invalid
3
ns
tWHAX2 Trailing Edge of WR to DPLD Address Invalid
(Note 4)
0
ns
tWHPV
Trailing Edge of WR to Port Output
Valid Using I/O Port Data Register
30
ns
) tDVMV
Data Valid to Port Output Valid Using Macrocell
Register Preset/Clear
(Note 3)
55
ns
t(s tWLMV
WR Valid to Port Output Valid Using
Macrocell Register Preset/Clear
(Note 2)
55
ns
uc Note: 1. Any input used to select an internal DSM function.
d 2. Assuming data is stable before active write signal.
ro 3. Assuming write is active before data becomes valid.
4. TWHAX2 is the address hold time for DPLD inputs that are used to generate Sector Select signals for internal DSM memory.
lete P Figure 35. Write Timing
Obso ADDRESS
- NON-MULTIPLEXED
) BUS
t(s DATA
NON-MULTIPLEXED
BUS
duc CSI
Obsolete Pro WR
tAVWL
ADDRESS
VALID
tSLWL
DATA
VALID
t WLWH
tDVWH
t WHDX
t WHAX
AI04909
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