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DSM2180F3 View Datasheet(PDF) - STMicroelectronics

Part Name
Description
MFG CO.
'DSM2180F3' PDF : 63 Pages View PDF
Figure 24. Reset (RESET) Timing
DSM2180F3
VCC
RESET
VCC(min)
tNLNH-PO
Power-On Reset
tOPR
tNLNH
tNLNH-A
Warm Reset
tOPR
AI02866b
Power On Reset, Warm Reset, Power-down
The Flash memory is reset to the Read Array
Power On Reset. Upon Power-up, the device re- mode upon Power-up. Sector Select FS0-FS7
quires a Reset (RESET) pulse of duration tNLNH-PO
after VCC is steady. During this time period, the de-
vice loads internal configurations, clears some of
must all be Low, Write Strobe (WR, CNTL0) High,
during Power On Reset for maximum security of
the data contents and to remove the possibility of
the registers and sets the Flash memory into Op-
erating mode. After the rising edge of Reset (RE-
t(s) SET), the device remains in the Reset mode for an
additional period, tOPR, before the first memory ac-
c cess is allowed.
a byte being written on the first edge of Write
Strobe (WR, CNTL0). Any Flash memory Write cy-
cle initiation is prevented automatically when VCC
is below VLKO.
du Table 19. Status During Power-On Reset, Warm Reset and Power-down Mode
ro Port Configuration
Power-On Reset
Warm Reset
Power-down Mode
P MCU I/O
Input mode
Input mode
Unchanged
solete PLD Output
Valid after internal PSD
configuration bits are
loaded
Valid
Depends on inputs to PLD
(addresses are blocked in
PD mode)
- Ob Register
Power-On Reset
) PMMR0 and PMMR2
Cleared to 0
ct(s OMC Flip-flop status
Cleared to 0 by internal
Power-On Reset
du All other registers
Cleared to 0
ro Warm Reset. Once the device is up and running,
P the device can be reset with a pulse of a much
te shorter duration, tNLNH. The same tOPR period is
needed before the device is operational after
le warm reset. Figure 24 shows the timing of the
o Power-up and warm reset.
s I/O Pin, Register and PLD Status at Reset. Ta-
bble 19 shows the I/O pin, register and PLD status
Oduring Power On Reset, warm reset and Power-
Warm Reset
Power-down Mode
Unchanged
Unchanged
Depends on .re and .pr
equations
Depends on .re and .pr
equations
Cleared to 0
Unchanged
Programming In-Circuit using JTAG ISP
In-System Programming (ISP) can be performed
through the JTAG signals on Port C. This serial in-
terface allows programming of the entire DSM de-
vice or subsections (i.e. only Flash memory but not
the PLDs) without and participation of the DSP. A
blank DSM device soldered to a circuit board can
be completely programmed in 10 to 20 seconds.
The basic JTAG signals; TMS, TCK, TDI, and
down mode. PLD outputs are always valid during TDO form the IEEE-1149.1 interface. The DSM
warm reset, and they are valid in Power On Reset device does not implement the IEEE-1149.1
once the internal device Configuration bits are Boundary Scan functions. The DSM uses the
loaded. This loading of the device is completed JTAG interface for ISP only. However, the DSM
typically long before the VCC ramps up to operat- device can reside in a standard JTAG chain with
ing level. Once the PLD is active, the state of the other JTAG devices as it will remain in BYPASS
outputs are determined by the PSDsoft Express mode while other devices perform Boundary
equations.
Scan.
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