DSM2180F3 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
DSM2180F3
STMicroelectronics
'DSM2180F3' PDF : 63 Pages View PDF
DSM2180F3
ISP programming time can be reduced as much as
30% by using two more signals on Port C, TSTAT
and TERR in addition to TMS, TCK, TDI and TDO.
See Table 20. The FlashLINKTM JTAG program-
ming cable available from STMicroelectronics for
$59USD and PSDsoft Express software that is
available at no charge from www.psdst.com is all
that is needed to program a DSM device using the
parallel port on any PC or laptop.
By default, the four pins on Port C are enabled for
the basic JTAG signals TMS, TCK, TDI, and TDO
on a blank device (and as shipped from factory)
See Application Note AN1153 for more details on
JTAG In-System Programming (ISP).
case, a single PLD input from Ports B, C, or D
must be dedicated to switch the Port C pins from I/
O mode back to ISP mode at any time. It is recom-
mended to physically connect this dedicated PLD
input pin to the JEN\ output signal from the Flash-
link cable when multiplexing JTAG signals. See
Application Note AN1153 for details.
Method 3 is rarely used to control JTAG pin oper-
ation. The DSP can set the port C pins to function
as JTAG ISP by setting the JTAG Enable bit in a
register of the csiop block, but as soon as the DSM
chip is reset, the csiop block registers are cleared,
which turns off the JTAG-ISP function. Controlling
JTAG pins using this method is not recommended.
Standard JTAG Signals. The standard JTAG
signals (TMS, TCK, TDI, and TDO) can be en- Table 20. JTAG Port Signals
abled by any of three different conditions that are
logically ORed. When enabled, TDI, TDO, TCK,
Port C Pin JTAG Signals
Description
and TMS are inputs, waiting for a JTAG serial
command from an external JTAG controller device
t(s) (such as FlashLINK or Automated Test Equip-
ment). When the enabling command is received,
c TDO becomes an output and the JTAG channel is
u fully functional inside the device. The same com-
d mand that enables the JTAG channel may option-
ro ally enable the two additional JTAG signals,
TSTAT and TERR.
P The following symbolic logic equation specifies the
te conditions enabling the four basic JTAG signals
le (TMS, TCK, TDI, and TDO) on their respective
o Port C pins. For purposes of discussion, the logic
s label JTAG_ON is used. When JTAG_ON is true,
b the four pins are enabled for JTAG operation.
O When JTAG_ON is false, the four pins can be
- used for general device I/O as specified in PSD-
) soft Express. JTAG_ON can become true by any
t(s of three different ways as shown:
uc JTAG_ON =
d 1. PSDsoft Express Pin Configuration -OR-
ro 2. PSDsoft Express PLD equation -OR-
P 3. DSP writes to register in csiop block
lete Method 1 is most common. This is when the JTAG
o pins are selected in PSDsoft Express to be “dedi-
s cated” JTAG pins. They can always transmit and
breceive JTAG information because they are “full-
Otime” JTAG pins.
PC0
TMS
Mode Select
PC1
TCK
Clock
PC3
TSTAT
Status
PC4
TERR
Error Flag
PC5
TDI
Serial Data In
PC6
TDO
Serial Data Out
JTAG Extensions. TSTAT and TERR are two
JTAG extension signals (must be used as a pair)
enabled by a command received over the four
standard JTAG signals (TMS, TCK, TDI, and
TDO) by PSDsoft Express. They are used to
speed Program and Erase cycles by indicating
status on device pins instead of having to scan the
status out serially using the standard JTAG chan-
nel. See Application Note AN1153.
TERR indicates if an error has occurred when
erasing a sector or programming a byte in Flash
memory. This signal goes Low (active) when an
Error condition occurs.
TSTAT behaves the same as Ready/Busy de-
scribed previously. TSTAT is inactive logic 1 when
the device is in Read mode (Flash memory con-
tents can be read). TSTAT is logic 0 when Flash
memory Program or Erase cycles are in progress.
TSTAT and TERR can be configured as open-
drain type signals with PSDsoft Express. This fa-
cilitates a wired-OR connection of TSTAT signals
from multiple DSM2180F3 devices and a wired-
Method 2 is used only when the JTAG pins are
multiplexed with general I/O functions. For de-
signs that need every I/O pin, the JTAG pins may
be used for general I/O when they are not used for
ISP. However, when JTAG pins are multiplexed
with general I/O functions, the designer must in-
clude a way to get the pins back into JTAG mode
OR connection of TERR signals from those same
devices. This is useful when several devices are
“chained” together in a JTAG environment. PSD-
soft Express puts TSTAT and TERR signals to
open-drain by default. Click on 'Properties' in the
JTAG-ISP window of PSDsoft Express to change
to standard CMOS push-pull. It is recommended
when it is time for JTAG operations again. In this
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