DSM2180F3 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
DSM2180F3
STMicroelectronics
'DSM2180F3' PDF : 63 Pages View PDF
DSM2180F3
Table 28. CPLD Macrocell Synchronous Clock Mode Timing
Symbol
Parameter
Conditions
-90
Min
Max
Fast PT
Aloc
Turbo
Off
Slew
Rate1 Unit
Maximum Frequency
External Feedback
1/(tS+tCO)
30.30
MHz
fMAX
Maximum Frequency
Internal Feedback
(fCNT)
1/(tS+tCO–10)
43.48
MHz
Maximum Frequency
Pipelined Data
1/(tCH+tCL)
50.00
MHz
tS
Input Setup Time
15
Add 2 Add 10
ns
tH
Input Hold Time
0
ns
tCH
Clock High Time
Clock Input
10
ns
tCL
Clock Low Time
Clock Input
10
) tCO
Clock to Output Delay
Clock Input
18
t(s tARD
CPLD Array Delay
Any Macrocell
16
c tMIN
Minimum Clock Period 2
tCH+tCL
20
du Note: 1. Fast Slew Rate output available on PB3-PB0, and PD2-PD0.
ro 2. CLKIN (PD1) tCLCL = tCH + tCL .
P Table 29. CPLD Macrocell Asynchronous Clock Mode Timing
olete Symbol
Parameter
Conditions
-90
Min
Max
bs Maximum Frequency
External Feedback
1/(tSA+tCOA)
26.32
t(s) - O fMAXA
Maximum Frequency
Internal Feedback
(fCNTA)
1/(tSA+tCOA–10)
35.71
c Maximum Frequency
u Pipelined Data
1/(tCHA+tCLA)
41.67
rod tSA
Input Setup Time
8
P tHA
Input Hold Time
12
te tCHA
Clock Input High Time
12
le tCLA
Clock Input Low Time
12
so tCOA
Clock to Output Delay
30
ObtARDA
CPLD Array Delay
Any Macrocell
16
Add 2
ns
Sub 2 ns
ns
ns
PT
Aloc
Turbo
Off
Slew
Rate
Unit
MHz
MHz
MHz
Add 2 Add 10
ns
ns
Add 10
ns
Add 10
ns
Add 10 Sub 2 ns
Add 2
ns
tMINA
Minimum Clock Period
1/fCNTA
28
ns
50/63
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