DSM2180F3 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

MFG CO.

DSM2180F3

DSM (Digital Signal Processor System Memory) for analog devices ADSP-218X family (5 V supply)

STMicroelectronics 

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DSM2180F3

Figure 5. Block Diagram

SECURITY

INTERNAL ADDR, DATA, CONTROL BUS LINKED TO DSP

DSM2180F3

LOCK

DSP SYSTEM

PAGE REG

FLASH MEMORY

MEMORY

fs7

fs6

fs5

DSP

ADDR

AD0

AD1

DECODE PLD

(DPLD)

FS0-7

fs4

fs3

fs2

fs1

fs0

8 SEGMENTS, 16 KB

128 KBytes TOTAL

DSP

DATA

PA0

PA1

PA2

AD2

PA3

AD3

PA4

AD4

RUNTIME CONTROL

PA5

AD5

AD6

CSIOP

CSIOP REGISTER FILE

PA6

PA7

AD7

POWER MANAGEMENT

AD8

AD9

AD10

EXTERNAL

EXTERNAL CHIP SELECTS, ESC0-2

I/O PORT

AD11

CHIP SELECTS

3 OPTIONAL OUTPUTS TO PORT D

PB0

AD12

PB1

AD13

AD14

AD15

) PC2

t(s PC7

c DSP

u CONTROL

d CNTL0

ro CNTL1

CNTL2

P PD0

PD1

PD2

solete RST\

COMPLEX PLD

(CPLD)

AND

ARRAY

A AAAA AAA

B BBBB BBB

B BBBB BBB

C CCCC CCC

16 OUTPUT MICRO<>CELLS

BBB BBBBB

CCC CC CCC

16 INPUT

MICRO<>CELLS

ALLO-

CATOR

PIN FEEDBACK

NODE FEEDBACK

JTAG-ISP

TO ALL AREAS

OF CHIP

PB2

PB3

PB4

PB5

PB6

PB7

I/O PORT

PC0

PC1

PC3

PC4

PC5

PC6

AI04911

b Programmable Logic (PLDs)

- O The DSM family contains two PLDS that may op-

) tionally run in Turbo or Non-Turbo mode. PLDs op-

t(s erate faster (less propagation delay) while in

Turbo mode but consume more power than Non-

c Turbo mode. Non-Turbo mode allows the PLDs to

u automatically go to standby when no inputs are

d change to conserve power. The Turbo mode set-

ro ting is controlled at runtime by DSP software.

P Decode PLD (DPLD). This is programmable log-

te ic used to select one of the eight individual Flash

memory segments or the group of control registers

le within the DSM device. The DPLD can also option-

o ally drive external chip select signals on Port D

s pins. DPLD input signals include: DSP address

band control signals, Page Register outputs, DSM

OPort Pins, CPLD logic feedback.

for making small peripheral devices (shifters,

counters, state machines, etc.) that are accessed

directly by the DSP with little overhead. DPLD in-

puts include DSP address and control signals,

Page Register outputs, DSM Port Pins, and CPLD

feedback.

OMCs: The general structure of the CPLD is simi-

lar in nature to a 22V10 PLD device with the famil-

iar sum-of-products (AND-OR) construct. True

and compliment versions of 64 input signals are

available to a large AND array. AND array outputs

feed into a multiple product-term OR gate within

each OMC (up to 10 product-terms for each

OMC). Logic output of the OR gate can be passed

on as combinatorial logic or combined with a flip-

flop within in each OMC to realize sequential logic.

OMCs can be used as a buried nodes with feed-

Complex PLD (CPLD). This programmable logic

is used to create both combinatorial and sequen-

back to the AND array or OMC output can be rout-

ed to pins on Port B or PortC.

tial general purpose logic. The CPLD contains 16 IMCs: Inputs from pins on Port B or Port C are

Output Macrocells (OMCs) and 16 Input Macro- routed to IMCs for conditioning (clocking or latch-

cells (IMCs). PSD macrocell registers are unique ing) as they enter the chip, which is good for sam-

in that that have direct connection to the DSP data pling and debouncing inputs. Alternatively, IMCs

bus allowing them to be loaded and read directly can pass Port input signals directly to PLD inputs

by the DSP at runtime. This direct access is good

8/63

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