External Memory Expansion Port (Port A)
Table 3-13 DRAM Out-of-Page and Refresh Timings, Four Wait States1, 2 (continued)
No.
Characteristics3
Symbol
Expression
20 MHz4
Min Max
30 MHz4
Min Max
Unit
165 RAS assertion to CAS deassertion
tCSH
2.75 × TC − 4.0 133.5
—
87.7
—
ns
166 CAS assertion pulse width
tCAS
1.25 × TC − 4.0 58.5
—
37.7
—
ns
167 RAS assertion to CAS assertion
tRCD
1.5 × TC ± 2
73.0
77.0
48.0
52.0
ns
168 RAS assertion to column address valid tRAD
1.25 × TC ± 2
60.5
64.5
39.7
43.7
ns
169 CAS deassertion to RAS assertion
tCRP
2.25 × TC − 4.0 108.5
—
71.0
—
ns
170 CAS deassertion pulse width
tCP
1.75 × TC − 4.0 83.5
—
54.3
—
ns
171 Row address valid to RAS assertion
tASR
1.75 × TC − 4.0 83.5
—
54.3
—
ns
172 RAS assertion to row address not valid tRAH
1.25 × TC − 4.0 58.5
—
37.7
—
ns
173 Column address valid to CAS
assertion
tASC
0.25 × TC − 4.0 8.5
—
4.3
—
ns
174 CAS assertion to column address not
tCAH
1.75 × TC − 4.0 83.5
—
54.3
—
ns
valid
175 RAS assertion to column address not
tAR
3.25 × TC − 4.0 158.5
—
104.3
—
ns
valid
176 Column address valid to RAS
deassertion
tRAL
2 × TC − 4.0
96.0
—
62.7
—
ns
177 WR deassertion to CAS assertion
tRCS
1.5 × TC − 3.8 71.2
—
46.2
—
ns
178 CAS deassertion to WR assertion
tRCH
0.75 × TC − 3.7 33.8
—
21.3
—
ns
179 RAS deassertion to WR assertion
tRRH
0.25 × TC − 3.7 8.8
—
4.6
—
ns
180 CAS assertion to WR deassertion
tWCH
1.5 × TC − 4.2 70.8
—
45.8
—
ns
181 RAS assertion to WR deassertion
tWCR
3 × TC − 4.2 145.8
—
95.8
—
ns
182 WR assertion pulse width
tWP
4.5 × TC − 4.5 220.5
—
145.5
—
ns
183 WR assertion to RAS deassertion
tRWL
4.75 × TC − 4.3 233.2
—
154.0
—
ns
184 WR assertion to CAS deassertion
tCWL
4.25 × TC − 4.3 208.2
—
137.4
—
ns
185 Data valid to CAS assertion (write)
tDS
2.25 × TC − 4.0 108.5
—
71.0
—
ns
186 CAS assertion to data not valid (write)
tDH
1.75 × TC − 4.0 83.5
—
54.3
—
ns
187 RAS assertion to data not valid (write)
tDHR
3.25 × TC − 4.0 158.5
—
104.3
—
ns
3-28
DSP56364 Technical Data, Rev. 4.1
Freescale Semiconductor