DSP56300FM View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
MFG CO.
'DSP56300FM' PDF : 148 Pages View PDF
External Memory Expansion Port (Port A)
Table 3-16 DRAM Out-of-Page and Refresh Timings, Fifteen Wait States1, 2 (continued)
No.
Characteristics3
Symbol
Expression
Min Max Unit
173 Column address valid to CAS assertion
tASC
0.75 × TC − 4.0
3.5
—
ns
174 CAS assertion to column address not valid
tCAH
6.25 × TC − 4.0
58.5 —
ns
175 RAS assertion to column address not valid
tAR
9.75 × TC − 4.0
93.5 —
ns
176 Column address valid to RAS deassertion
tRAL
7 × TC − 4.0
66.0
—
ns
177 WR deassertion to CAS assertion
178 CAS deassertion to WR4 assertion
179 RAS deassertion to WR4 assertion
tRCS
tRCH
tRRH
5 × TC − 3.8
46.2
—
ns
1.75 × TC − 3.7
13.8 —
ns
0.25 × TC − 2.0
0.5
—
ns
180 CAS assertion to WR deassertion
tWCH
6 × TC − 4.2
55.8
—
ns
181 RAS assertion to WR deassertion
tWCR
9.5 × TC − 4.2
90.8
—
ns
182 WR assertion pulse width
tWP
15.5 × TC − 4.5
150.5 —
ns
183 WR assertion to RAS deassertion
tRWL
15.75 × TC − 4.3 153.2 —
ns
184 WR assertion to CAS deassertion
tCWL
14.25 × TC − 4.3 138.2 —
ns
185 Data valid to CAS assertion (write)
tDS
8.75 × TC − 4.0
83.5 —
ns
186 CAS assertion to data not valid (write)
tDH
6.25 × TC − 4.0
58.5 —
ns
187 RAS assertion to data not valid (write)
tDHR
9.75 × TC − 4.0
93.5 —
ns
188 WR assertion to CAS assertion
tWCS
9.5 × TC − 4.3
90.7
—
ns
189 CAS assertion to RAS assertion (refresh)
tCSR
1.5 × TC − 4.0
11.0
—
ns
190 RAS deassertion to CAS assertion (refresh)
tRPC
4.75 × TC − 4.0
43.5 —
ns
191 RD assertion to RAS deassertion
tROH
15.5 × TC − 4.0
151.0 —
ns
192 RD assertion to data valid
193 RD deassertion to data not valid3
tGA
14 × TC − 5.7
— 134.3 ns
tGZ
0.0
—
ns
194 WR assertion to data active
0.75 × TC − 0.3
7.2
—
ns
195 WR deassertion to data high impedance
0.25 × TC
—
2.5 ns
1 The number of wait states for out-of-page access is specified in the DCR.
2 The refresh period is specified in the DCR.
3 RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ.
4 Either tRCH or tRRH must be satisfied for read cycles.
3-34
DSP56364 Technical Data, Rev. 4.1
Freescale Semiconductor
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