E28F200BVB80 View Datasheet(PDF) - Intel
Part Name
Description
MFG CO.
'E28F200BVB80' PDF : 55 Pages View PDF
E
2-MBIT SmartVoltage BOOT BLOCK FAMILY
4.5 AC Characteristics—Commercial (Continued)
Prod
BV-80
BV-120
Sym
Parameter
VCC 3.3 ± 0.3V(5) 5V ± 10%(7) 3.3 ± 0.3V(5) 5V ± 10%(7) Unit
Load 50 pF
100 pF
50 pF
100 pF
Notes Min Max Min Max Min Max Min Max
tAVAV Read Cycle Time
150
80
180
120
ns
tAVQV Address to Output Delay
150
80
180
120 ns
tELQV CE# to Output Delay
2
150
80
180
120 ns
tPHQV RP# to Output Delay
0.8
0.45
0.8
0.45 µs
tGLQV OE# to Output Delay
2
90
40
90
40 ns
tELQX CE# to Output in Low Z
3
0
0
0
0
ns
tEHQZ CE# to Output in High Z
3
45
20
45
25 ns
tGLQX OE# to Output in Low Z
3
0
0
0
0
ns
tGHQZ OE# to Output in High Z
3
45
20
45
20 ns
tOH Output Hold from Address,
3
0
0
0
0
ns
CE#, or OE# Change,
Whichever Occurs First
tELFL CE# Low to BYTE# High or 3
0
0
0
0
ns
tELFH Low
tAVFL Address to BYTE# High or
3
5
5
5
5 ns
Low
tFLQV BYTE# to Output Delay
3,4
150
80
180
120 ns
tFHQV
tFLQZ BYTE# Low to Output in
3
High Z
60
30
60
30 ns
tPLPH Reset Pulse Width Low
8 150
60
150
60
ns
tPLQZ RP# Low to Output High-Z
150
60
150
60 ns
NOTES:
1. See AC Input/Output Reference Waveform for timing measurements.
2. OE# may be delayed up to tCE–tOE after the falling edge of CE# without impact on tCE.
3. Sampled, but not 100% tested.
4. tFLQV, BYTE# switching low to valid output delay will be equal to tAVQV, measured from the time DQ15/A–1 becomes valid.
5. See Test Configuration (Figure 14), 3.3 V Standard Test component values.
6. See Test Configuration (Figure 14), 5 V High-Speed Test component values.
7. See Test Configuration (Figure 14), 5 V Standard Test component values.
8. The specification tPLPH is the minimum time that RP# must be held low in order to product a valid reset of the device.
SEE NEW DESIGN RECOMMENDATIONS
35
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