E28F200BVB80 View Datasheet(PDF) - Intel
Part Name
Description
MFG CO.
'E28F200BVB80' PDF : 55 Pages View PDF
E
2-MBIT SmartVoltage BOOT BLOCK FAMILY
NOTES:
1. Read timing characteristics during program and erase operations are the same as during read-only operations. Refer to AC
Characteristics during read mode.
2. The on-chip WSM completely automates program/erase operations; program/erase algorithms are now controlled internally
which includes verify and margining operations.
3. Refer to command definition table for valid AIN. (Table 7)
4. Refer to command definition table for valid DIN. (Table 7)
5. Program/erase durations are measured to valid SRD data (successful operation, SR.7 = 1).
6. For boot block program/erase, RP# should be held at VHH or WP# should be held at VIH until operation completes
successfully.
7. Time tPHBR is required for successful locking of the boot block.
8. Sampled, but not 100% tested.
9. See Test Configuration (Figure 14), 3.3 V Standard Test component values.
10. See Test Configuration (Figure 14), 5 V High-Speed Test component values.
11. See Test Configuration (Figure 14), 5 V Standard Test component values.
1
VIH
ADDRESSES (A)
VIL
VIH
CE# (E)
2
AIN
t AVAV
3
AIN
tAVWH
4
tWHAX
VIL
VIH
t
ELWL
OE# (G)
tWHEH
VIL
VIH
WE# (W)
tWHWL
t WHQV1,2,3,4
VIL
VIH
DATA (D/Q)
VIL
High Z
DIN
6.5V VHH
t PHWL
RP# (P) VIH
tWLWH
t DVWH
t WHDX
DIN
tPHHWH
VIL
VIH
WP# VIL
VPPH2
VPPH1
V (V)
PP
VPPLK
VIL
t VPWH
NOTES:
1. VCC Power-Up and Standby.
2. Write program or Erase Set-Up Command.
3. Write Valid Address and Data (Program) or Erase Confirm Command.
4. Automated Program or Erase Delay.
5. Read Status Register Data.
6. Write Read Array Command.
5
6
Valid
SRD
DIN
tQVPH
t QVVL
Figure 17. AC Waveforms for Write Operations (WE#–Controlled Writes)
SEE NEW DESIGN RECOMMENDATIONS
0530_17
39
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