E910.27A View Datasheet(PDF) - ELMOS Semiconductor AG
Part Name
Description
MFG CO.
'E910.27A' PDF : 50 Pages View PDF
- Preliminary -
E910.27A
7.2 Linear Regulators
7.2.1 Internal Power Supply
The internal high PSRR power supply allows the E910.27 to operate from typically 4.5V up to 40V input vol-
tage (VSA), while drawing a constant very low quiescent current (ISHTD). This allows the use in automotive
K30 systems. It is always on and supports the internal regulators, thermal protection circuits, undervoltage
lockout circuits and error logic's with stable reference voltages and currents.
7.2.2 VSM Regulator
The power supply block contains also a short and thermal protected low quiescent current 5V low drop linear
regulator (VSM). It will be switched on via a high level at Pin ENPS. Output VSM can provide at minimum
10mA to an external load (e.g. stand by circuits).
Due to the very wide input level range from 0V to VSMAX, and CMOS compatible thresholds the ENPS input
can be driven by controllers, bus transceivers (e.g. CAN), K15D applications and used for power
sequencing.
In SMPS operating mode (SMON=true) the linear regulator powers the internal SMPS circuits. When the
input voltage VSA goes below about 4V and therefore VSM drops down to the level VCLRH the E910.27
enters into undervoltage lockout state, the internal P-channel MOS transistor is switched off and the ERR
output goes low. Bypass VSM with a good quality capacitor (CSM) to the small signal ground.
7.3 Device Quiscent Currents
Mode
Shutdown (Idle)
VSM ON (linear regulator on, not externally loaded)
SMPS ON (not switching)
ENPS
0
1
1
SMON
0
0
1
Device Quiescent current
ISHTD
IVSMST
IDQS
7.4 DRV Regulator
The E910.27 contains a high side hysteretic regulator (CDRV) that controls its output to a voltage of VDRV
below the positive high side driver input voltage VSP. This regulator limits the internal P-channel MOS transi-
stor gate swing, provides high gate charge / discharge currents, high switching frequency and allowing high
input voltage operation without exceeding the internal P-channel MOS transistor gate source breakdown vol-
tage. If VDRV drops due any case to its lookout voltage VDRVL the ERR output will be set and internal P-
channel MOS transistor is switched off. Bypass CDRV always with a good quality temperature stable cera-
mic capacitor between VSP and CDRV, otherwise the chip may be damaged. To avoid substrate currents in
case of very high temperatures and a fast falling edge of the input voltage a Schottky diode between CDRV
and PGND may be necessary.
7.5 Error Output
Pin ERR indicates fault conditions of the E910.27. These conditions are:
• Under voltage lockout (VSM < VCRH)
• Driver voltage low (VDRV < VDRVL)
• Chip over temperature (Tj > KTMPS)
ELMOS Semiconductor AG
Specification 17 / 50
03SP0357E.00 05.09.2006
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