E910.27A View Datasheet(PDF) - ELMOS Semiconductor AG
Part Name
Description
MFG CO.
'E910.27A' PDF : 50 Pages View PDF
- Preliminary -
E910.27A
7.7.3 Watchdog Timing
When the voltage on the delay capacitor CDLY has reached VWUD and pin WEN was set high, the
watchdog circuit is enabled and discharges CDLY with a constant current IWDD. If there is no rising edge
detected at the watchdog input, CDLY will be discharge down to VWLD, then PWGD output will be set low
and CDLY will be charged again with the current IWDC until VCDLY reaches VWUD and pin PWGD will be
set high (high impedance) again.
If a watchdog pulse, rising edge at watchdog input WDI, occurs during the discharge period, CDLY is char-
ged again and the PWGD output stays high. After VCDLY has reached VWUD, the periodical behaviour
starts once more.
The watchdog timing is defined by the charging and discharging time of the external capacitor CDLY and
can be calculated as follows:
TWDTR = (VWUD − VWLD) ⋅ CDLY
IWDD
TWDP = (VWUD − VWLD )⋅ (IWDC + IWDD ) ⋅ CDLY
IWDC ⋅ IWDD
TWDL = (VWUD −VWLD ) ⋅ CDLY
IWDC
[2]
VOUT
VWDI
t
VCDLY
VPWGD
TWDTR
TWDP
TWDL
t
VWUD
VWLD
t
t
Figure 7.7.3-1: Watchdog Behaviour, Time Response
Use hard wired coding of WDE on the pc-board, because changing the mode during operating is not allo-
wed.
ELMOS Semiconductor AG
Specification 20 / 50
03SP0357E.00 05.09.2006
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