E910.27A View Datasheet(PDF) - ELMOS Semiconductor AG
Part Name
Description
MFG CO.
'E910.27A' PDF : 50 Pages View PDF
- Preliminary -
E910.27A
• SMON input pin low
One or more errors switch the ERR output into high impedance. If the ERR pin is not used, it should be con-
nected to ground. The open drain output can be wired with other signals.
7.6 Reference Multiplexer
A high flexibel feature of the E910.27 is its internal reference multiplexer. Due to the externally selectable
MUX the user can choose between two internal precise temperature compensated or an user provided
external reference. Via an external reference voltage at pin RFEX the output voltage or output current of the
SMPS circuit can be controlled (e.g. for LED dimming applications or synchronous output voltage ramp up).
Keep in mind that in case of disabling VSM (ENPS=false) the ESD input structures of pins RFEX, RSEL, and
RLEV will clamp to ground. Input signals in this mode leads to malfunction of the E910.27 and are therefore
not allowed. In any case floating of the three pins must be avoided. A save way to supply the logic levels for
the multiplexer is for logically „false“ connect to ground and for logically „true“ connect to VSM. Use hard
wired coding on the pc-board, because changing the mode during operating is not allowed.
VCMP connected to
VR1 (internal)
VR2 (internal)
VREXT (external)
RFEX
-
-
Ex. Ref Input
RLEV
0
1
0
RSEL
0
0
1
7.7 Power Good, Reset Generation and Watchdog Circuitry
7.7.1 PWRGOOD Block
Depending on external wiring the PWRGOOD circuit can provide POWER-GOOD, RESET or WATCHDOG
behaviour. The PWGD pin open drain output can be wired „OR“ to other E910.27. If the PWGD pin is not
used it should be connected to GND.
If the external reference input (RFEX) is selected via the MUX (RSEL=true), the whole PWRGOOD block is
automaticly disabled and the PWGD output stays low. For correct behaviour of the PWGD pin, there must be
a minimum input voltage at VSA of 4V.
7.7.2 Power Good and Reset Timing
If the switcher feedback voltage VFB decreases 15% out of nominal regulation value, the external capacitor
CDLY at pin CDLY will be discharged fast by the reset generator and pin PWGD is set low. If feedback vol-
tage VFB rises above the reset threshold, VREF-10%, CDLY will be charged with a constant current IWDC.
After the power on reset time TRST the voltage on capacitor CDLY reaches VRUD and the PWGD output
will be set high (high impedance) again. The value of the power on reset time TRST can be set within a wide
range depending on the capacitance value of CDLY.
The delay time of power on reset is defined by the charging time of the external capacitor CDLY and can be
calculated as follows:
TRST = (VRUD − VRLD ) ⋅ CDLY
IWDC
[1]
For power good behaviour of the circuit only, e.g. in case of ramp up sequencing of multiple power supplies,
the delay capacitor CDLY is omitted. PWGD output than will react instantaneously (within TPWGD).
ELMOS Semiconductor AG
Specification 18 / 50
03SP0357E.00 05.09.2006
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