E910.27A View Datasheet(PDF) - ELMOS Semiconductor AG
Part Name
Description
MFG CO.
'E910.27A' PDF : 50 Pages View PDF
- Preliminary -
E910.27A
VDROP _ OP
≈
VRIPPLE
2
[7]
At light output loads, the choke current is discontinuous, takes the E910.27 to switch at lower frequencies
and decreasing the internal P-channel MOS transistor's gate drive and switching losses. Under most circum-
stances in discontinuous mode the on-time will be fixed to the minimum on-time of TONM. If the choke (LCK)
inductance value is small or the current sense resistor (RS) is large the current limit will be reached before
the minimum on-time (TONM), terminating the on-time and overwrite it.
If the impedance of the feedback divider is too high, or the choke (LCK) inductance is too large, or the output
capacitance (COUT) is too high and equivalent series resistance (ESR) is too low, then the internal P-chan-
nel MOS transistor remains on longer than the minimum on-time (TONM) until the output capacitor charges
beyond the voltage comparators (VCMP) hysteresis of about VHYST and causing the controller to operate in
hysteretic mode. Operating in hysteretic mode results in lower switching frequency operation.
VHYST
≈ 4mV
⋅ 1 +
RFB1
RFB 2
[8]
The E910.27 requires a certain ESR value for proper operation. The transition to hysteretic mode occurs at
the critical output capacitor ESR:
C _ ESRCRITICAL
≈ VHYST
I RIPPLE
[9]
In the above equation IRIPPLE is the choke ripple current and can be approached, for duty cycle less than
33%, by:
( ) I RIPPLE ≈
VINPUT
− VOUTPUT − IOUTMAX ⋅ (RS + RDSON )
LCK
⋅ TONM
[10]
Where TONM is the minimum on-time for minimum on-time control, or in case of duty cycle greater than
33%:
I RIPPLE
≈ (VOUTPUT + Vd DSW ) ⋅ TOFFM
LCK
[11]
Where TOFFM is the minimum off-time for minimum off-time mode.
7.8.5 Leading Edge Blanking
A leading edge blanking timer (TBLK) avoids an erratic operation through spikes at RSIN input while switch-
ing on the internal P-channel MOS transistor. The same timer suppresses also a quasi-analogue operation
of the internal P-channel MOS transistor by means of too small gate drive pulses. Too small gate pulses lead
to internal overheating and the complete SMPS is switched off.
ELMOS Semiconductor AG
Specification 24 / 50
03SP0357E.00 05.09.2006
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