E910.27A View Datasheet(PDF) - ELMOS Semiconductor AG
Part Name
Description
MFG CO.
'E910.27A' PDF : 50 Pages View PDF
- Preliminary -
E910.27A
8 Design Information
8.1 Design Guidelines
External component selection is driven by output to input voltage ratio (duty cycle), ripple current and maxi-
mum output load. The circuit design is an iterative process and must be carefully proved by testing of your
prototype. First calculate the appropriate duty cycle range for your circuit, then proceed as follows.
8.1.1 Output Voltage Setting
The step down converter´s output voltage is set using the following equation, where RFB2 is connected
between the VFB pin and SGND, and RFB1 is connected between VOUTPUT and the VFB pin.
RFB1 = VOUTPUT − 1 ⋅ RFB2
VREF
[13]
Where VREF is 200mV, 1.2V or externally by user provided in the range of 0V to 1.3V.
Output voltage ripple causes the output voltage to be higher or lower than set by the resistor divider at the
feedback pin VFB. If the application runs with minimum on-time, the ripple (half of the peak to peak value)
adds to the output voltage. In the case of working with minimum off-time, the output voltage is lower by the
amount of ripple (half of the peak to peak value) at the output.
The input bias current at VFB loads the divider, therefore RFB2 should not be set too high-valued resistor to
obtain high accuracy. A divider current of 120µA or higher is recommend. The feedback voltage line can be
sensitive to noise. Avoid inductive coupling to the choke or the switching node, by keeping the VFB trace
away from these areas.
In some applications, depending on board layout, the capacitance may be too high from pin VFB to GND. In
this case, the internal comparator may not switch fast enough to operate with the minimum on-time or the
minimum off-time given in this data sheet. For such applications a small feedforward capacitor (CFF) should
be added in parallel with RFB1 to speed up the internal voltage comparator. On the other hand in some
applications, depending on board layout, a small capacitor (some pF) in parallel to RFB2 might be necessary
for stable operation. But this changes the operating frequency range too.
8.1.2 Current Sense Resistor Selection
In case of SMPS ramping up, heavy output load, or shorted output, the current sense comparator CCMP lim-
its the peak switching current to VCLIM/RS, where RS is the value of the current sense resistor and VCLIM
is the current sense threshold. Minimising the peak switching current will increase efficiency and reduce the
size and cost of external components. But, since available output current is a function of the peak switching
current the peak limit must not be set too low.
A good value is setting the peak current limit to 1.20 times the maximum load current by calculating the cur-
rent sense resistor to:
.
RS ≤
VCLIM MIN
1.20
⋅
IOUT
MAX
+
I RIPPLE
2
[14]
This takes the normal coke's inductance value tolerance into account. The maximum RMS current in con-
tinuous operating mode is (take “r” from the calculations below):
ELMOS Semiconductor AG
Specification 26 / 50
03SP0357E.00 05.09.2006
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