EM78862C View Datasheet(PDF) - ELAN Microelectronics
Part Name
Description
MFG CO.
'EM78862C' PDF : 42 Pages View PDF
EM78862C
8-Bit RISC Type Microprocessor
6.1.8 R8 (Port8) --- Page 0
Bit 7
P87
Bit 6
P86
Bit 5
P85
Bit 4
P84
Bit 3
P83
Bit 2
P82
Bit 1
P81
Bit 0
P80
Bit 0 ~ Bit 7 (P80 ~ P87): 8-bit PORT8 (0 ~ 7) I/O data register
You can use IOC8 Page 0 register to define each bit as input
or output.
6.1.9 R9 (Port9) --- Page 0
Bit 7
P97
Bit 6
P96
Bit 5
P95
Bit 4
P94
Bit 3
P93
Bit 2
P92
Bit 1
P91
Bit 0
P90
Bit 0 ~ Bit 7 (P90 ~ P97): 8-bit PORT9 (0 ~ 7) I/O data register
You can use IOC9 Page 0 register to define each bit as input
or output.
6.1.10 RA (Mode Control Register) --- Page 0
Bit 7
IDLE
Bit 6
PLLEN
Bit 5
CLK1
Bit 4
CLK0
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
WDTEN
Bit 0 (WDTEN): Watch dog control register
0/1 → disable/enable
You can use WDTC instruction to clear watch dog timer. The timer's
clock source is 32.768k/2 Hz. If the prescaler is assigned to TCC, the
watchdog timer will time out by (1/32768) * 2 * 256 = 15.616ms. If
assigned to WDT, the time out time will be longer than 15.616ms
depending on the prescaler ratio.
Bit 1 ~ Bit 3: Not used
Bit 4 ~ Bit 5 (CLK0 ~ CLK1): Main clock = 3.579Mhz, CLK0 ~ CLK1 are set to ‘1’.
Bit 6 (PLLEN): PLL enable control bit
0/1 → disable/enable
This is the CPU mode control register. If PLL is enabled, CPU will
operate under Normal mode (high frequency, main clock). Otherwise,
it will run under Green mode (low frequency, 32.768kHz).
The relation between 32.768K and 3.579M crystal is explained in the
following figure.
10 •
Product Specification (V2.1) 07.13.2005
(This specification is subject to change without further notice)
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