EM78862C View Datasheet(PDF) - ELAN Microelectronics
Part Name
Description
MFG CO.
'EM78862C' PDF : 42 Pages View PDF
EM78862C
8-Bit RISC Type Microprocessor
NOTE
1. The controller can drive the LCD directly. LCD block is made up of LCD driver,
display RAM, segment output pins, common output pins, and LCD operating
voltage converter capacitor pins. LCD voltage converter pins C1A & C1B should
be connected with a C1 (1uF) capacitor. C14 & C45 need to be connected with
1uF capacitors to the ground.
2. The number of common and frame frequency are determined by LCD mode
Register RE PAGE0 Bit 0~ Bit 1.
3. LCD driver can be regulated into different levels of driving mode (refer to Section
6.2.4, “IOC6 PAGE2” register).
4. The basic structure contains a timing control which uses the basic frequency
32.768kHz to generate the proper timing for display access. RE PAGE0 register
is a command register for LCD driver and display. The LCD display (disable,
enable, blanking) is controlled by RE PAGE0 Bit 2 ~ Bit 3 and the driving duty is
decided by RE PAGE Bit 0 ~ Bit 1. LCD display data is stored in LCD RAM which
address and data access are controlled by registers RA PAGE1 and RB PAGE1.
Bits 5 ~ Bit 7: Not used
6.1.16 RE (DATA RAM Address8 ~ 10) --- Page 1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
RAM_A10 RAM_A9 RAM_A8
Bit 0 ~ Bit 2 (RAM_A8~RAM_A10): Data RAM address (Address8 to Address10) for
RAM reading (can be addressed from 0h to 4FFh
maximum).
Bit 3 ~ Bit 7: Not used.
6.1.17 RF (INTERRUPT Flags*)
Bit 7
Bit 6
Bit 5
Bit 4
-
-
INT2
INT1
* "1" = interrupt request; "0" = non-interrupt
Bit 3
INT0
Bit 2
CNT2
Bit 1
CNT1
Bit 0
TCIF
Bit 0 (TCIF): TCC timer overflow interrupt flag
When TCC timer overflows, interrupt is set.
Bit 1 (CNT1): Counter1 timer overflow interrupt flag
When Counter1 timer overflows, interrupt is set.
Bit 2 (CNT2): Counter2 timer overflow interrupt flag
When Counter2 timer overflows, interrupt is set.
Bit 3 (INT0): External INT0 pin interrupt flag
When PORT70, PORT71, PORT72, or PORT73 encounters a falling
edge trigger signal, CPU sets this bit to interrupt.
Product Specification (V2.1) 07.13.2005
(This specification is subject to change without further notice)
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