EM78862C View Datasheet(PDF) - ELAN Microelectronics
Part Name
Description
MFG CO.
'EM78862C' PDF : 42 Pages View PDF
EM78862C
8-Bit RISC Type Microprocessor
6.8 Interrupt
The EM78862C IC has two types of internal interrupts which are falling edge triggered:
TCC timer overflow interrupt (internal)
Two 8-bit counters overflow interrupt
If these interrupt sources change signal from high to low, the RF register will generate
'1' flag to the corresponding register if IOCF register is enabled.
RF is the interrupt status register which records the interrupt request in flag bit. IOCF is
the interrupt mask register. Global interrupt is enabled by ENI instruction and is
disabled by DISI instruction. When one of the interrupts (if enabled) is generated, the
next instruction will be fetched from address 008H. Once in the interrupt service
routine, the source of the interrupt can be determined by polling the flag bits in the RF
register.
Four external interrupt pins, i.e., INT0, INT1, INT2, & INT3, and three internal interrupts
are available:
External interrupt signals (INT0, INT1 and INT2) are from Port7 Bit 0 to Bit 7. If
IOCF is enabled, then these signals will activate interrupt. Otherwise, these signals
will be treated as general input data.
Internal signals include TCC, CNT1, and CNT2.
After a reset, the next instruction will be fetched from Address 000H and the
hardware interrupt is 008H.
After timeout, TCC will go to Address 008H when in GREEN mode or NORMAL
mode. When in IDLE mode, TCC will go to Address 008H run interrupt service. After
RETI instruction jump to the next instruction after “SLEP” instruction. These two
conditions will set a RF flag.
The interrupt flag bit must be cleared in software before leaving the interrupt
service routine in order to prevent and avoid recursive interrupts.
NOTE
It is very important to save ACC, R3, and R5 when processing an interrupt as illustrated
below:
24 •
Product Specification (V2.1) 07.13.2005
(This specification is subject to change without further notice)
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