EM78862C
8-Bit RISC Type Microprocessor
6.3 TCC/WDT Prescaler
An 8-bit counter is available as prescaler for the TCC or WDT. The prescaler is
available only to either the TCC or WDT at a time.
An 8-bit counter is made available for TCC or WDT as determined by the status of Bit
3 (PAB) of CONT register.
The prescaler ratio is described in Section 6.2.2, CONT (Control Register).
The TCC/WDT circuit diagram is shown in Fig. 10 below.
Both TCC and prescaler are cleared by instructions.
The prescaler will be cleared by the WDTC and SLEP instructions when running
under WDT mode.
However, the prescaler cannot be cleared by SLEP instruction when running under
TCC mode.
NOTE
CONT is a readable and writable register.
CLK = Fosc/2
Data Bus
16.38kHz
or RC/2
OSCSEL
W DT
W DTE
0
1
SYNC
2 Cycles
TCC(R1)
1
0
TS
0
1
PAB
8-BIT Counter
TCC Overflow
Interrupt
PAB
8-to-1 MUX
0
1
MUX
PSR0~PSR2
PAB
W DT Timeout
Fig. 8 TCC WDT Block Diagram
20 •
Product Specification (V2.1) 07.13.2005
(This specification is subject to change without further notice)