EM78862C
8-Bit RISC Type Microprocessor
Bit 4 (INT1): External INT1 pin interrupt flag
When PORT74, PORT75, or PORT76 encounters a falling edge trigger
signal, CPU sets this bit to interrupt.
Bit 5 (INT2): External INT2 pin interrupt flag
When PORT77 encounters a falling s this bit to interrupt.
Bits 6 ~ 7: Not used.
6.1.18 R10 ~ R1F and R20 ~ R3F (General Purpose Registers)
R10 ~ R1F & R20 ~ R3F (Banks 0~3) are general-purpose registers
6.2 Special Purpose Registers
6.2.1 A (Accumulator, ACC)
Internal data transfer, or instruction operand holding. This is not an addressable
register.
6.2.2 CONT (Control Register)
Bit 7
INT_EDG
E
Bit 6
INT
Bit 5
TS
Bit 4
-
Bit 3
PAB
Bit 2
PSR2
Bit 1
PSR1
Bit 0
PSR0
Bit 0 ~ Bit 2 (PSR0~PSR2): TCC/WDT pre-scale bits
PSR2
0
0
0
0
1
1
1
1
PSR1
0
0
1
1
0
0
1
1
PSR0
0
1
0
1
0
1
0
1
TCC Rate
1:2
1:4
1:8
1:16
1:32
1:64
1:128
1:256
WDT Rate
1:1
1:2
1:4
1:8
1:16
1:32
1:64
1:128
Bit 3 (PAB): Prescaler assigned bit
0/1 → TCC/WDT
Bit 4:
Not used
Bit 5 (TS): TCC signal source
0 → Instruction clock
1 → 16.384kHz or RC/2
Instruction clock = MCU Clock/2. Refer to RA Bit 4 ~ Bit 6 Page 0 for PLL
(Section 6.1.10) and Main Clock selection (Section 6.3, Fig.8).
16 •
Product Specification (V2.1) 07.13.2005
(This specification is subject to change without further notice)