EM78862C View Datasheet(PDF) - ELAN Microelectronics
Part Name
Description
MFG CO.
'EM78862C' PDF : 42 Pages View PDF
EM78862C
8-Bit RISC Type Microprocessor
Bit 6 (INT): INT enable flag
0 → interrupt masked by DISI or hardware interrupt
1 → interrupt enabled by ENI/RETI instructions
Bit 7 (INT_EDGE): interrupt edge type of P77
0 → P77's interrupt source is a rising edge and falling edge signal.
1 → P77's interrupt source is a falling edge signal.
CONT register is readable (CONTR) and writable (CONTW).
6.2.3 IOC5 (Port8 & Port9 Port Switch Register) --- Page 0
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
P9SH
Bit 2
P9SL
Bit 1
P8SH
Bit 0
P8SL
Bit 0 (P8SL) : Switch low nibble I/O PORT8 or LCD segment output for share pins
SEGnn/P8n pins
0 → select normal P80 ~ P83 for low nibble PORT8
1 → select SEG64 ~ SEG67 output for LCD SEGMENT output
Bit 1 (P8SH): Switch high nibble I/O PORT8 or LCD segment output for share pins
SEGnn/P8n
0 → select normal P84 ~ P87 for high nibble PORT8
1 → select SEG68 ~ SEG71 output for LCD SEGMENT output
Bit 2 (P9SL): Switch low nibble I/O PORT9 or LCD segment output for share pins
SEGnn/P9n pins
0 → select normal P90 ~ P93 for low nibble PORT9
1 → select SEG72 ~ SEG75 output for LCD SEGMENT output
Bit 3 (P9SH): Switch high nibble I/O PORT9 or LCD segment output for share pins
SEGnn/P9n pins
0 → select normal P94 ~ P97 for high nibble PORT9
1 → select SEG76 ~ SEG79 output for LCD SEGMENT output.
Bits 4 ~ 7: Not used
6.2.4 IOC7 (Port7 I/O Control Register) --- Page 0
Bit 7
IOC77
Bit 6
IOC76
Bit 5
IOC75
Bit 4
IOC74
Bit 3
IOC73
Bit 2
IOC72
Bit 1
IOC71
Bit 0
IOC70
Bit 0 ~ Bit 7(IOC70 ~ IOC77):PORT7(0~7) I/O direction control register
0 → set the relative I/O pin as output
1 → set the relative I/O pin as input (high impedance)
6.2.5 IOC8 (Port8 I/O Control Register) --- Page 0
Bit 7
IOC87
Bit 6
IOC86
Bit 5
IOC85
Bit 4
IOC84
Bit 3
IOC83
Bit 2
IOC82
Bit 1
IOC81
Bit 0
IOC80
Product Specification (V2.1) 07.13.2005
(This specification is subject to change without further notice)
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