EM78P569 View Datasheet(PDF) - ELAN Microelectronics
Part Name
Description
MFG CO.
'EM78P569' PDF : 58 Pages View PDF
EM78P569
8-bit OTP Micro-controller
PAGE1 (Counter1 data register)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
CN17 CN16 CN15 CN14 CN13 CN12 CN11 CN10
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
Bit 0 ~ Bit 7 (CN10 ~ CN17) : Counter1's buffer that user can read and write.
Counter1 is a 8-bit up-counter with 8-bit prescaler that user can use RC PAGE1 to preset and read the
counter.(write preset) After a interruption , it will reload the preset value.
Example for writing :
MOV 0x0C, A ; write the data at accumulator to counter1 (preset)
Example for reading :
MOV A, 0x0C ; read the data at counter1 to accumulator
PAGE2(LSB 8-bit Multiplication result)
7
MR7
6
MR6
5
MR5
4
MR4
3
MR3
2
MR2
1
MR1
0
MR0
R/W
R/W
R/W
R/W R/W
R/W
R/W
R/W
Bit 0 ~ Bit 7 (MR0 ~ MR7) : Multiplication result data
The multiplier can make a multiplication with X*Y. The multiplicator data buffer X is ACC(acculator) and
the multiplicand data buffer Y is RB PAGE2. The LSB 8-bit of maximum 24 bit multiplication result MR
will be stored in RC PAGE2.
RC PAGE2 = MR(0~7) = LSB 8-bit (X*Y)
PAGE3 : (undefined) not allowed to use
RD (LCD control, Counter2 data, PWM1,2 duty latch)
PAGE0 (LCD driver control bits)
7
6
5
4
3
2
1
0
- VERSEL PHO
1
- LCD_C1 LCD_C0 LCD_M
R/W-0 R/W-0 R/W-0
R/W-0 R/W-0 R/W-0
Bit 0 (LCD_M) : LCD operation method including duty and frame frequency
Bit 1 ~ Bit 2 (LCD_C0 ~ LCD_C1) : LCD display control
LCD_C1 LCD_C0 LCD_M LCD Display Control Duty Bias
0
0
0 change duty
1/4
1/3
1 Disable(turn off LCD) 1/2
1/3
0
1
: Blanking
:
:
1
1
: LCD display enable
:
:
Ps. To change the display duty must set the "LCD_C1 ,LCD_C0" to "00".
The controller can drive LCD directly. The LCD block is made up of common driver, segment driver,
display LCD RAM, common output pins, segment output pins and LCD operating power supply. The basic
structure contains a timing control. This timing control uses the basic frequency 32.768KHz to generate the
proper timing for different duty and display access.
RD PAGE0 Bit 0 ~ Bit 2 are LCD control bits for LCD driver. These LCD control bits determine the duty,
the number of common and the frame frequency. The LCD display (disable, enable, blanking) is controlled
by Bit 1 and Bit 2. The driving duty is decided by Bit 0. The display data is stored in LCD RAM which
address and data access controlled by registers R5 PAGE1 and R6 PAGE1.
User can regulate the contrast of LCD display by IOC5 PAGE0 Bit 0 ~ Bit 3 (BIAS0 ~ BIAS3). Up to 16
levels contrast is convenient for better display.
Bit 3, Bit 7 : (undefined) not allowed to use
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
24
8/19/2004 V4.4
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