EM78P569 View Datasheet(PDF) - ELAN Microelectronics
Part Name
Description
MFG CO.
'EM78P569' PDF : 58 Pages View PDF
EM78P569
8-bit OTP Micro-controller
Trigger edge as the table
Signal
Trigger
TCC
Time out
COUNTER1 Time out
COUNTER2 Time out
INT0
Falling
Rising edge
INT1
Falling edge
INT2
Falling edge
DETO
Falling edge
Falling and rising edge
R10~R3F (General Purpose Register)
R10~R3F (Banks 0 ~ 3) : all are general purpose registers.
VII.3 Special Purpose Registers
A (Accumulator)
Internal data transfer, or instruction operand holding
It's not an addressable register.
CONT (Control Register)
7
6
5
4
3
2
1
0
P70EG
INT
TS RETBK PAB PSR2 PSR1 PSR0
Bit 0 ~ Bit 2 (PSR0 ~ PSR2) : TCC/WDT prescaler bits
PSR2 PSR1 PSR0 TCC rate WDT rate
0
0
0
1:2
1:1
0
0
1
1:4
1:2
0
1
0
1:8
1:4
0
1
1
1:16
1:8
1
0
0
1:32
1:16
1
0
1
1:64
1:32
1
1
0
1:128
1:64
1
1
1
1:256
1:128
Bit 3(PAB) : Prescaler assignment bit
0/1 TCC/WDT
Bit 4(RETBK) : Return value backup control for interrupt routine
0 disable/enable
When this bit is set to 1, the CPU will store ACC,R3 status and R5 PAGE automatically after an interrupt is
triggered. And it will be restored after instruction RETI. When this bit is set to 0, the user need to store ACC,
R3 and R5 PAGE in user program.
Bit 5(TS) : TCC signal source
0 internal instruction cycle clock
1 16.384kHz
Bit 6 (INT) : INT enable flag
0 interrupt masked by DISI or hardware interrupt
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
27
8/19/2004 V4.4
Share Link: 
