EVAL-AD5100EBZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
EVAL-AD5100EBZ
Analog Devices
'EVAL-AD5100EBZ' PDF : 36 Pages View PDF
Standard Watchdog Mode
In the default standard watchdog mode, if WDI remains either
high or low for longer than the timeout period, tWD, a RESET
pulse is generated in an attempt to allow the system processor
to reestablish the WDI signal. The RESET pulses continue
indefinitely until a valid watchdog signal, a rising or falling edge
signal at the WDI, is received. The internal watchdog timer
clears whenever a reset is asserted. The standard WDI and
RESET timing diagrams are shown in Figure 13.
tWDI
WDI
AD5100
Advanced Watchdog Mode
The AD5100 can be programmed into an advanced watchdog
mode. In this mode, if WDI remains either high or low for longer
than the timeout period, tWD, a RESET pulse is generated, as per
standard mode. However, if the WDI input remains inactive after
three such RESET pulses, concurrent with the fourth RESET pulse,
SHDN is also asserted. SHDN is released after 1 second. These
actions repeat indefinitely (unless action is taken by the user), if
the processor is not responding. The advanced WDI and RESET
timing diagrams are shown in Figure 14.
tWD
tWDR
tWD
tWDR
RESET
RESET PULSE
CONTINUOUS PULSES UNTIL WATCHDOG AWAKES
tWDR = WATCHDOG-INITIATED RESET PULSE WIDTH
tWDI = WATCHDOG PULSE WIDTH
tWD = WATCHDOG PROGRAMMABLE TIME
Figure 13. Standard Watchdog—Pulsing Reset Until Watchdog Awakes
tWDI
WDI
tWD
tWDR
tWD
tWDI
RESET
1 RESET PULSE
3 RESET PULSES
tWD_SHDN
SHDN
SHUTDOWN AT 4TH RESET PULSE
RELEASE AFTER 1s
Figure 14. Advanced Watchdog—SHDN Asserted After Three Trials of Resetting the Watchdog (SHDN Released After 1 Second and the Cycle Repeats)
Rev. A | Page 17 of 36
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