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EVAL-AD5100EBZ View Datasheet(PDF) - Analog Devices

Part Name
Description
MFG CO.
'EVAL-AD5100EBZ' PDF : 36 Pages View PDF
AD5100
POWER REQUIREMENTS
INTERNAL POWER, VREG
The AD5100 internal power, VREG, is derived from V1MON and
becomes active when V2MON reaches 2.2 V. V2MON is used to turn
AD5100 on and off with a different behavior depending on the
V2MON monitoring mode selection.
By default, the AD5100 turns on when the voltage at V2MON rises
above the logic threshold, V2MON_ON. When V2MON falls below the
logic threshold, V , 2MON_OFF AD5100 turns off 2 seconds after
SHDN is deasserted. Note that AD5100 requires 5 μs to start up
and that V1MON must be applied before V2MON. Extension of the
AD5100 turn-off allows the system to complete any housekeeping
tasks before the system is powered off. Figure 18 shows the
default V2MON and VREG waveforms.
Rising Edge Triggered Wake-Up Mode
If rising edge triggered wake-up V2MON mode is selected instead,
the AD5100 does not turn off when V2MON returns to a logic low.
To configure the part into rising edge triggered mode, set the
V2MON off threshold register, Register 0x04[3:1], to 1001.
In this mode, once the part is powered on, it can only be powered
down by an I2C power-down instruction or by removing the
supply on the V1MON pin. To power down the part over the I2C
bus while in rising edge triggered mode, the user must first
ensure that the software power down feature is enabled.
Register 0x18[3] = 0: enable software power-down feature
Register 0x18[3] =1: disable software power-down feature
The user must then write to Register 0x17[0], to actually power
down the AD5100.
Register 0x17[0] = 0: AD5100 not in software power-down
Register 0x17[0] = 1: power down AD5100
This feature is for applications that use a wake-up signal.
tGLITCH
V2MON
V2MON_ON*
V2MON,IH
t2SD_HOLD*
SHDN
V2MON_OFF*
V2MON_ON*
V2MON_OFF*
t2SD_DELAY*
t2SD_HOLD*
t2SD_DELAY*
t2SD_DELAY*
tVREG_ON_DELAY
tVREG_OFF_DELAY
VREG
tVREG_OFF_DELAY
NOTES
1. 6V < V1MON < 30V
2. * = PROGRAMMABLE
Figure 18. Internal Power VREG vs. V2MON Timing Diagrams (Default)
Rev. A | Page 21 of 36
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