EVAL-AD5100EBZ View Datasheet(PDF) - Analog Devices

Part Name

Description

MFG CO.

EVAL-AD5100EBZ

System Management IC with Factory Programmed Quad Voltage Monitoring and Supervisory Functions

Analog Devices 

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AD5100

Register

Address

0x16

0x17

0x18

0x19

Read/

Write

R/W

R/W

R/W

Read-

only

Permanently

Settable

No

No

No

No

Register Name and Bit Description

Special function 1

Bit No. Description

[0]

Reserved

[1]

Reserved

[2]

0: software assertion of SHDN pin is inactive

1: pulls SHDN pin low

[3]

0: override of permanent settings inactive

1: override of permanent settings active

[7:4]

Reserved

Special function 2

Bit No. Description

[0]

0: software power-down of AD5100 inactive

1: software power-down of AD5100 active2

[7:1]

Reserved

Disable special functions3

Bit No. Description

[0]

0: allows override of any of the registers in memory except

Register 0x16 Bit[2:0] and Register 0x17 Bit[0]

1: disables override of any of the registers in memory except

Register 0x16 Bit[2:0] and Register 0x17 Bit[0]

[1]

Reserved

[2]

Reserved

[3]

0: allows software power-down function

1: disables software power-down function

[4]

0: allows software assertion of SHDN pin

1: disables software assertion of SHDN pin

[7:5]

Reserved

Fault detect and status

(Bits[3:0] are level triggered bits that indicate the current state of the

comparators monitoring the V1MON and V2MON input pins; Bits[6:4] are edge

triggered fault detection bits that indicate what error conditions were present

when a SHDN event occurred)

Bit No. Description

[0]

1 = V2MON input < V2MON off threshold

[1]

1 = V2MON input > V2MON on threshold

[2]

1 = V1MON input < V1MON UV threshold

[3]

1 = V1MON input > V1MON OV threshold

[6:4]

000: none

001: V1MON UV only

010: V1MON OV only

011: never occurred

100: V2MON below off only (default)

101: V1MON UV and V2MON below off both occurred

110: V1MON OV and V2MON below off both occurred

111: never occurred

[7]

Reserved

NonOTP Power-On

Default1

0x00

0x00

0x00

0x40

1 Default settings of AD5100-0 evaluation model only.

2 V2MON must be 0 V (that is, V2MON must be configured in edge sensitive mode) for software power-down.

3 These register bits are set only. To clear them, the AD5100 must be power cycled. In some cases, the AD5100 can be connected to an I2C bus with lots of activity.

Setting these bits is an added means of ensuring that any erroneous activity on the bus does not cause AD5100 special functions to become active.

Rev. A | Page 25 of 36

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