AD5100
Register
Address
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x15
Read/
Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Permanently
Settable
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Register Name and Bit Description
V2MON turn-on triggered SHDN hold (t2SD_HOLD)
Bit No. Description
[2:0]
Three bits used to program V2MON tON triggered SHDN hold time
[7:3]
Reserved
V2MON turn-off triggered SHDN delay (t2SD_DELAY)
Bit No. Description
[2:0]
Three bits used to program V2MON tOFF triggered SHDN delay time
[7:3]
Reserved
RESET hold (tRS_HOLD)
Bit No. Description
[2:0]
Three bits used to program RESET hold time
[7:3]
Reserved
Watchdog timeout (tWD)
Bit No. Description
[2:0]
Three bits used to program watchdog timeout time
[7:3]
Reserved
RESET configuration
Bit No. Description
[0]
0: RESET is active when SHDN is active
1: RESET is not active when SHDN is active
[1]
0: RESET active low
1: RESET active high
[2]
0: enables V4MON under threshold, causing RESET
1: prevents V4MON under threshold from causing RESET (for V4OUT
applications)
[3]
0: floating WDI does not activate RESET
1: floating WDI activates RESET
[7:4]
Reserved
SHDN rail voltage configuration
Bit No. Description
[2:0]
Reserved
[3]
0: SHDN rail = V1MON
1: SHDN rail = VREG
[7:4]
Reserved
Watchdog mode
Bit No. Description
[2:0]
Reserved
[3]
0: standard mode
1: advanced mode
[7:4]
Reserved
Program lock (inhibit further programming)
Bit No. Description
[2:0]
Reserved
[3]
Reserved
[7:4]
Reserved
NonOTP Power-On
Default1
0x00 (10 ms)
0x00 (100 ms)
0x00 (200 ms)
0x00 (1500 ms)
0x00
0x00
0x00
0x00
Rev. A | Page 24 of 36