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EVAL-AD5100EBZ View Datasheet(PDF) - Analog Devices

Part Name
Description
MFG CO.
'EVAL-AD5100EBZ' PDF : 36 Pages View PDF
AD5100
The RESET signal is asserted and maintained except when it is
triggered by the WDI, which is described in the Watchdog Input
section. The RESET signal is released after the programmable
hold time, tRS_HOLD.
As shown in Figure 17, the RESET output is push-pull
configured with the rail voltage of V3MON.
V3MON
M1
RESET
M2
Figure 17. Reset Output
SHUTDOWN WARNING, SHDNWARN
An early shutdown warning is available for the system processor
to identify the source of failure and take appropriate action
before shutting down the external devices. Whenever the
voltage at V1MON is detected as overvoltage or undervoltage,
or the voltage at V2MON falls below the threshold, SHDNWARN
outputs a Logic 0. If the processor sees a logic low on this pin,
the processor may issue an I2C read command to identify the
cause of failure reported in the fault detect/status register, at
Address 0x19. The processor may store the information in
external EEPROM as a record of failure history.
V4OUT OUTPUT
V4OUT is an open-drain output triggered by V4MON with a mini-
mum propagation delay, t . V4OUT_DELAY V4OUT can be used as a PWM
control over an external device or used as a monitoring signal.
Most applications using V4OUT require disabling of the V4MON
triggered reset function. This function is disabled by writing to
Register 0x0D[2], and it is possible to fix the value of this bit in
OTP memory.
Register 0x0D[2] = 0: enables V4MON under threshold to activate
RESET
Register 0x0D[2] = 1: prevents V4MON under threshold from
activating RESET
Rev. A | Page 20 of 36
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