EVAL-AD5252SDZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-AD5252SDZ' PDF : 28 Pages View PDF
AD5251/AD5252
Data Sheet
Parameter
DIGITAL INPUTS AND OUTPUTS
Input Logic High
Symbol
VIH
Input Logic Low
Output Logic High (SDA)
Output Logic Low (SDA)
WP Leakage Current
A0 Leakage Current
Input Leakage Current
(Other than WP and A0)
Input Capacitance5
POWER SUPPLIES
Single-Supply Power Range
Dual-Supply Power Range
Positive Supply Current
Negative Supply Current
VIL
VOH
VOL
IWP
IA0
II
CI
VDD
VDD/VSS
IDD
ISS
EEMEM Data Storing Mode Current
EEMEM Data Restoring Mode
Current6
Power Dissipation7
Power Supply Sensitivity
IDD_STORE
IDD_RESTORE
PDISS
PSS
DYNAMIC CHARACTERISTICS5, 8
Bandwidth –3 dB
Total Harmonic Distortion
VW Settling Time
Resistor Noise Voltage
Digital Crosstalk
BW
THD
tS
eN_WB
CT
Analog Coupling
CAT
Conditions
Min Typ1 Max Unit
VDD = 5 V, VSS = 0 V
2.4
VDD/VSS = 2.7 V/0 V or VDD/VSS = ± 2.5 V 2.1
VDD = 5 V, VSS = 0 V
RPULL-UP = 2.2 kΩ to VDD = 5 V, VSS = 0 V 4.9
RPULL-UP = 2.2 kΩ to VDD = 5 V, VSS = 0 V
WP = VDD
A0 = GND
VIN = 0 V or VDD
5
V
V
0.8
V
V
0.4
V
8
µA
3
µA
±1
µA
pF
VSS = 0 V
VIH = VDD or VIL = GND
VIH = VDD or VIL = GND, VDD = 2.5 V,
VSS = –2.5 V
VIH = VDD or VIL = GND
VIH = VDD or VIL = GND
VIH = VDD = 5 V or VIL = GND
ΔVDD = 5 V ± 10%
ΔVDD = 3 V ± 10%
2.7
±2.25
5
–5
5.5
V
±2.75 V
15
µA
–15 µA
35
mA
2.5
mA
0.075 mW
−0.025 +0.010 +0.025 %/%
–0.04 +0.02 +0.04 %/%
RAB = 1 kΩ
4
VA = 1 V rms, VB = 0 V, f = 1 kHz
0.05
VA = VDD, VB = 0 V
0.2
RWB = 500 Ω, f = 1 kHz
3
(thermal noise only)
VA = VDD, VB = 0 V, measure VW with
–80
adjacent RDAC making full-scale
change
Signal input at A1 and measure the
–72
output at W3, f = 1 kHz
MHz
%
µs
nV/√Hz
dB
dB
1 Typical values represent average readings at 25°C and VDD = 5 V.
2 Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum and minimum resistance wiper positions. R-DNL is the
relative step change from an ideal value measured between successive tap positions. Parts are guaranteed monotonic, except R-DNL of AD5252 1 kΩ version at VDD =
2.7 V, IW = VDD/R for both VDD = 3 V and VDD = 5 V.
3 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider, similar to a voltage output digital-to-analog converter. VA = VDD and VB = 0 V.
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
4 Resistor Terminal A, Terminal B, and Terminal W have no limitations on polarity with respect to each other.
5 Guaranteed by design and not subject to production test.
6 Command 0 NOP should be activated after Command 1 to minimize IDD_READ current consumption.
7 PDISS is calculated from IDD × VDD = 5 V.
8 All dynamic characteristics use VDD = 5 V.
Rev. D | Page 4 of 28
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