EVAL-AD5252SDZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-AD5252SDZ' PDF : 28 Pages View PDF
AD5251/AD5252
Data Sheet
Parameter
POWER SUPPLIES
Single-Supply Power Range
Dual-Supply Power Range
Positive Supply Current
Negative Supply Current
EEMEM Data Storing Mode
Current
EEMEM Data Restoring Mode
Current6
Power Dissipation7
Power Supply Sensitivity
DYNAMIC CHARACTERISTICS5, 8
–3 dB Bandwidth
Total Harmonic Distortion
VW Settling Time
Resistor Noise Voltage
Symbol
VDD
VDD/VSS
IDD
ISS
IDD_STORE
IDD_RESTORE
PDISS
PSS
BW
THDW
tS
eN_WB
Digital Crosstalk
CT
Analog Coupling
CAT
Conditions
Min Typ1
Max Unit
VSS = 0 V
2.7
±2.25
VIH = VDD or VIL = GND
5
VIH = VDD or VIL = GND, VDD = 2.5 V,
−5
VSS = −2.5 V
VIH = VDD or VIL = GND, TA = 0°C to 105°C
35
VIH = VDD or VIL = GND, TA = 0°C to 105°C
2.5
VIH = VDD = 5 V or VIL = GND
ΔVDD = 5 V ± 10%
ΔVDD = 3 V ± 10%
−0.005 +0.002
−0.010 +0.002
5.5
V
±2.75 V
15
µA
−15 µA
mA
mA
0.075 mW
+0.005 %/%
+0.010 %/%
RAB = 10 kΩ/50 kΩ/100 kΩ
VA = 1 V rms, VB = 0 V, f = 1 kHz
VA = VDD, VB = 0 V,
RAB = 10 kΩ/50 kΩ/100 kΩ
RAB = 10 kΩ/50 kΩ/100 kΩ,
code = midscale, f = 1 kHz
(thermal noise only)
VA = VDD, VB = 0 V, measure VW with
adjacent RDAC making full-scale
change
Signal input at A1 and measure
output at W3, f = 1 kHz
400/80/40
0.05
1.5/7/14
9/20/29
−80
−72
kHz
%
µs
nV/√Hz
dB
dB
1 Typical values represent average readings at 25°C and VDD = 5 V.
2 Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum and minimum resistance wiper positions. R-DNL is the
relative step change from an ideal value measured between successive tap positions. Parts are guaranteed monotonic, except R-DNL of AD5252 1 kΩ version at VDD = 2.7 V,
IW = VDD/R for both VDD = 3 V and VDD = 5 V.
3 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider, similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits
of ±1 LSB maximum are guaranteed monotonic operating conditions.
4 Resistor Terminal A, Terminal B, and Terminal W have no limitations on polarity with respect to each other.
5 Guaranteed by design and not subject to production test.
6 Command 0 NOP should be activated after Command 1 to minimize IDD_READ current consumption.
7 PDISS is calculated from IDD × VDD = 5 V.
8 All dynamic characteristics use VDD = 5 V.
Rev. D | Page 6 of 28
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