EVAL-AD5252SDZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-AD5252SDZ' PDF : 28 Pages View PDF
Data Sheet
AD5251/AD5252
INTERFACE TIMING CHARACTERISTICS
All input control voltages are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V. Switching
characteristics are measured using both VDD = 3 V and 5 V.
Table 3. Interface Timing and EEMEM Reliability Characteristics (All Parts)1
Parameter
Symbol
Conditions
Min Typ Max Unit
INTERFACE TIMING
SCL Clock Frequency
fSCL
tBUF Bus-Free Time Between Stop and Start
t1
tHD;STA Hold Time (Repeated Start)
t2
1.3
After this period, the first clock pulse is 0.6
generated.
400 kHz
µs
µs
tLOW Low Period of SCL Clock
t3
1.3
µs
tHIGH High Period of SCL Clock
t4
0.6
µs
tSU;STA Set-up Time for Start Condition
t5
0.6
µs
tHD;DAT Data Hold Time
t6
0
0.9 µs
tSU;DAT Data Set-up Time
t7
100
ns
tF Fall Time of Both SDA and SCL Signals
t8
300 ns
tR Rise Time of Both SDA and SCL Signals
t9
300 ns
tSU;STO Set-up Time for Stop Condition
t10
0.6
µs
EEMEM Data Storing Time
EEMEM Data Restoring Time at Power-On2
EEMEM Data Restoring Time upon Restore
Command or Reset Operation2
tEEMEM_STORE
tEEMEM_RESTORE1
tEEMEM_RESTORE2
VDD rise time dependent. Measure
without decoupling capacitors at VDD
and VSS.
VDD = 5 V.
26
ms
300
µs
300
µs
EEMEM Data Rewritable Time (Delay Time
After Power-On or Reset Before EEMEM
Can Be Written)
tEEMEM_REWRITE
540
µs
FLASH/EE MEMORY RELIABILITY
Endurance3
100
k cycles
Data Retention4
100
Years
1 Guaranteed by design; not subject to production test. See Figure 23 for location of measured values.
2 During power-up, all outputs are preset to midscale before restoring the EEMEM contents. RDAC0 has the shortest EEMEM data restoring time, whereas RDAC3 has the longest.
3 Endurance is qualified to 100,000 cycles per JEDEC Standard 22, Method A117, and measured at −40°C, +25°C, and +105°C; typical endurance at +25°C is 700,000
cycles.
4 Retention lifetime equivalent at junction temperature TJ = 55°C per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6 eV derates
with junction temperature in Flash/EE memory.
Rev. D | Page 7 of 28
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