EVAL-AD5680EB View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-AD5680EB' PDF : 20 Pages View PDF
Data Sheet
AD5680
SPECIFICATIONS
VDD = 4.5 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; VREF = VDD; all specifications TMIN to TMAX, unless otherwise noted.
Table 1.
Parameter
STATIC PERFORMANCE2
Resolution
Relative Accuracy
Differential Nonlinearity3
Zero-Code Error
Full-Scale Error
Offset Error
Gain Error
Zero-Code Error Drift
Gain Temperature Coefficient
DC Power Supply Rejection Ratio
OUTPUT CHARACTERISTICS3
Output Voltage Range
Output Voltage Settling Time
Slew Rate
Capacitive Load Stability
Output Noise Spectral Density4
Output Noise (0.1 Hz to 10 Hz)4
Total Harmonic Distortion (THD)4
Digital-to-Analog Glitch Impulse
Digital Feedthrough
DC Output Impedance
Short-Circuit Current4
REFERENCE INPUT
Reference Current
Reference Input Range5
Reference Input Impedance
LOGIC INPUTS3
Input Current
VINL, Input Low Voltage
VINH, Input High Voltage
Pin Capacitance
POWER REQUIREMENTS
VDD
IDD (Normal Mode)
VDD = 4.5 V to 5.5 V
POWER EFFICIENCY
IOUT/IDD
B Grade1
Min Typ Max
18
±32 ±64
±1
±2
2
10
−0.2 −1
±10
±1.5
±2
±2.5
−100
0
VDD
80
85
1.5
2
10
80
25
−80
5
0.2
0.5
30
40
75
0.75
VDD
125
±2
0.8
2
3
4.5
5.5
325 450
85
Unit
Conditions/Comments
Bits
LSB
LSB
LSB
mV
% FSR
mV
% FSR
μV/°C
ppm
dB
Measured in 50 Hz system bandwidth
Measured in 300 Hz system bandwidth
All 0s loaded to DAC register
All 1s loaded to DAC register
Of FSR/°C
DAC code = midscale; VDD = 5 V ± 10%
V
μs
V/μs
nF
nF
nV/√Hz
μV p-p
dB
nV-s
nV-s
Ω
mA
¼ to ¾ scale change settling to ±8 LSB,
RL = 2 kΩ; 0 pF < CL < 200 pF
¼ to ¾ scale
RL = ∞
RL = 2 kΩ
DAC code = midscale, 10 kHz
DAC code = midscale
VREF = 2 V ± 300 mV p-p, f = 200 Hz
1 LSB change around major carry
VDD = 5 V
μA
VREF = VDD = 5 V
V
kΩ
μA
All digital inputs
V
VDD = 5 V
V
VDD = 5 V
pF
V
All digital inputs at 0 V or VDD
DAC active and excluding load current
μA
VIH = VDD and VIL = GND
%
ILOAD = 2 mA, VDD = 5 V
1 Temperature range for B version is −40°C to +105°C, typical at +25°C.
2 DC specifications tested with the outputs unloaded, unless otherwise stated. Linearity calculated using a reduced code range of 2048 to 260,096.
3 Guaranteed by design and characterization; not production tested.
4 Output unloaded.
5 Reference input range at ambient where maximum DNL specification is achievable.
Rev. C | Page 3 of 20
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