EVAL-AD5680EB View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-AD5680EB' PDF : 20 Pages View PDF
AD5680
Data Sheet
TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 2.
VDD = 4.5 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
t11
t2
t3
t4
t5
t6
t7
t8
t9
t10
tUPDATE
Limit at TMIN, TMAX
VDD = 4.5 V to 5.5 V
33
13
13
13
5
4.5
0
33
13
0
250
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
μs min
Conditions/Comments
SCLK cycle time
SCLK high time
SCLK low time
SYNC to SCLK falling edge setup time
Data setup time
Data hold time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time
SYNC rising edge to SCLK fall ignore
SCLK falling edge to SYNC fall ignore
Minimum update period
1 Maximum SCLK frequency is 30 MHz at VDD = 4.5 V to 5.5 V.
SCLK
SYNC
DIN
t10
t1
t9
t8
t4
t3
t2
t7
DB23
t6
t5
DB0
Figure 2. Serial Write Operation
Rev. C | Page 4 of 20
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