EVAL-AD5687RSDZ View Datasheet(PDF) - Analog Devices

Part Name

Description

MFG CO.

EVAL-AD5687RSDZ

Dual, 16-/12-Bit nanoDAC+ with 2 ppm/°C Reference, SPI Interface

Analog Devices 

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Data Sheet

LOAD DAC (HARDWARE LDAC PIN)

The AD5689R/AD5687R DACs have double buffered interfaces

consisting of two banks of registers: input registers and DAC

registers. The user can write to any combination of the input

registers. Updates to the DAC register are controlled by the

LDAC pin.

OUTPUT

AMPLIFIER

VREF

16-/12-BIT

DAC

VOUTX

LDAC

DAC

REGISTER

INPUT

REGISTER

SCLK

SYNC

SDIN

INTERFACE

LOGIC

SDO

Figure 47. Simplified Diagram of Input Loading Circuitry for a Single DAC

Instantaneous DAC Updating (LDAC Held Low)

LDAC is held low while data is clocked into the input register

using Command 0001. Both the addressed input register and

the DAC register are updated on the rising edge of SYNC, and

then the output begins to change (see Table 14 and Table 15).

AD5689R/AD5687R

updated by taking LDAC low after SYNC is taken high. The

update then occurs on the falling edge of LDAC.

LDAC MASK REGISTER

Command 0101 is reserved for a software LDAC mask function,

which allows the address bits to be ignored. A write to the DAC,

using Command 0101, loads the 4-bit LDAC mask register (DB3

to DB0). The default setting for each channel is 0; that is, the

LDAC pin works normally. Setting the selected bit to 1 forces the

DAC channel to ignore transitions on the LDAC pin, regardless

of the state of the hardware LDAC pin. This flexibility is useful

in applications where the user wishes to select which channels

respond to the LDAC pin.

The LDAC mask register gives the user extra flexibility and control

over the hardware LDAC pin (see Table 13). Setting an LDAC

bit (DB3, DB0) to 0 for a DAC channel means that the update

of this channel is controlled by the hardware LDAC pin.

Table 13. LDAC Overwrite Definition

Load LDAC Register

LDAC Bits

(DB3, DB0)

0

1

LDAC Pin

1 or 0

X1

LDAC Operation

Determined by the LDAC pin.

DAC channels update and override

the LDAC pin. DAC channels see the

LDAC pin as set to 1.

1 X = don’t care.

Deferred DAC Updating (LDAC Pulsed Low)

LDAC is held high while data is clocked into the input register

using Command 0001. Both DAC outputs are asynchronously

Table 14. 24-Bit Input Shift Register Contents for LDAC Operation1

DB23

(MSB) DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 to DB4

0

1

0

1

X

X

X

X

X

Command bits (C3 to C0)

Address bits, don’t care

Don’t care

1 X = don’t care.

DB0

DB3

DB2

DB1

(LSB)

DAC B

0

0

DAC A

Setting the LDAC bit to 1 overrides the LDAC pin

Table 15. Write Commands and LDAC Pin Truth Table1

Command Description

Hardware LDAC

Pin State

0001

Write to Input Register n

(dependent on LDAC)

VLOGIC

GND2

0010

Update DAC Register n with

contents of Input Register n

VLOGIC

GND

0011

Write to and update DAC Channel n VLOGIC

GND

Input Register Contents

Data update

Data update

No change

No change

Data update

Data update

DAC Register Contents

No change (no update)

Data update

Updated with input register contents

Updated with input register contents

Data update

Data update

1 A high-to-low hardware LDAC pin transition always updates the contents of the DAC register with the contents of the input register on channels that are not masked

(blocked) by the LDAC mask register.

2 When the LDAC pin is permanently tied low, the LDAC mask bits are ignored.

Rev. B | Page 23 of 28

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