EVAL-AD7676CB View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-AD7676CB' PDF : 20 Pages View PDF
AD7676
t9
RESET
BUSY
DATABUS
t8
CNVST
Figure 12. RESET Timing
For other applications, conversions can be automatically initiated.
If CNVST is held LOW when BUSY is LOW, the AD7676
controls the acquisition phase and then automatically initiates a
new conversion. By keeping CNVST LOW, the AD7676 keeps
the conversion process running by itself. It should be noted that
the analog input has to be settled when BUSY goes LOW. Also,
at power-up, CNVST should be brought LOW once to initiate the
conversion process. In this mode, the AD7676 could sometimes
run slightly faster than the guaranteed limit of 500 kSPS.
DIGITAL INTERFACE
The AD7676 has a versatile digital interface; it can be interfaced
with the host system by using either a serial or parallel interface.
The serial interface is multiplexed on the parallel databus. The
AD7676 digital interface also accommodates both 3 V or 5 V
logic by simply connecting the OVDD supply pin of the AD7676
to the host system interface digital supply. Finally, by using the
OB/2C input pin, either twos complement or straight binary
coding can be used.
The two signals CS and RD control the interface. When at least
one of these signals is HIGH, the interface outputs are in high
impedance. Usually, CS allows the selection of each AD7676 in
multicircuit applications and is held LOW in a single AD7676
design. RD is generally used to enable the conversion result on
the databus.
CS = RD = 0
t1
CNVST
BUSY
t3
t10
t4
t11
DATABUS
PREVIOUS CONVERSION DATA
NEW DATA
Figure 13. Master Parallel Data Timing for Reading
(Continuous Read)
PARALLEL INTERFACE
The AD7676 is configured to use the parallel interface (Figure 13)
when the SER/PAR is held LOW. The data can be read either
after each conversion, which is during the next acquisition phase,
or during the following conversion as shown, respectively, in
Figures 14 and 15. When the data is read during the conversion,
however, it is recommended that it be read-only during the first
half of the conversion phase. That avoids any potential feedthrough
between voltage transients on the digital interface and the most
critical analog conversion circuitry.
CS
RD
BUSY
DATABUS
CURRENT
CONVERSION
t12
t13
Figure 14. Slave Parallel Data Timing for Reading
(Read after Conversion)
CS = 0
CNVST,
t1
RD
BUSY
t4
t3
DATABUS
PREVIOUS
CONVERSION
t12
t13
Figure 15. Slave Parallel Data Timing for Reading (Read
during Conversion)
The BYTESWAP pin allows a glueless interface to an 8-bit bus.
As shown in Figure 16, the LSB byte is output on D[7:0] and the
MSB is output on D[15:8] when BYTESWAP is LOW. When
BYTESWAP is HIGH, the LSB and MSB bytes are swapped and
the LSB is output on D[15:8] and the MSB is output on D[7:0].
By connecting BYTESWAP to an address line, the 16-bit data
can be read in two bytes on either D[15:8] or D[7:0].
CS
RD
BYTE
HI-Z
PINS D[15:8]
HI-Z
PINS D[7:0]
HIGH BYTE
t12
LOW BYTE
LOW BYTE
t12
HIGH BYTE
HI-Z
t13
HI-Z
Figure 16. 8-Bit Parallel Interface
–14–
REV. B
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