EVAL-AD7676CB View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-AD7676CB' PDF : 20 Pages View PDF
AD7676
External Clock Data Read During Conversion
Figure 20 shows the detailed timing diagrams of this method.
During a conversion, while both CS and RD are LOW, the result
of the previous conversion can be read. The data is shifted out,
MSB first, with 16 clock pulses, and is valid on both rising and
falling edges of the clock. The 16 bits have to be read before the
current conversion is complete. If that is not done, RDERROR is
pulsed HIGH and can be used to interrupt the host interface to
prevent incomplete data reading. There is no daisy chain feature
in this mode, and RDC/SDIN input should always be tied either
HIGH or LOW.
To reduce performance degradation due to digital activity, a fast
discontinuous clock of at least 18 MHz is recommended to ensure
that all the bits are read during the first half of the conversion
phase. For this reason, this mode is more difficult to use.
MICROPROCESSOR INTERFACING
The AD7676 is ideally suited for traditional dc measurement
applications supporting a microprocessor and ac signal processing
applications interfacing to a digital signal processor. The AD7676
is designed to interface either with a parallel 8-bit or 16-bit wide
interface or with a general-purpose Serial Port or I/O Ports on a
microcontroller. A variety of external buffers can be used with
the AD7676 to prevent digital noise from coupling into the ADC.
The following sections illustrate the use of the AD7676 with
an SPI-equipped microcontroller, and the ADSP-21065L and
ADSP-218x signal processors.
SPI Interface (MC68HC11)
Figure 22 shows an interface diagram between the AD7676 and an
SPI-equipped microcontroller, such as the MC68HC11. To accom-
modate the slower speed of the microcontroller, the AD7676 acts
as a slave device and data must be read after conversion. This mode
also allows the daisy chain feature. The convert command could
be initiated in response to an internal timer interrupt. The reading
of output data, one byte at a time if necessary, could be initiated
in response to the end-of-conversion signal (BUSY going LOW)
using an interrupt line of the microcontroller. The serial periph-
eral interface (SPI) on the MC68HC11 is configured for Master
Mode (MSTR) = 1, Clock Polarity Bit (CPOL) = 0, Clock Phase
Bit (CPHA) = 1, and SPI interrupt enable (SPIE) = 1 by writing
to the SPI Control Register (SPCR). The IRQ is configured for
edge-sensitive-only operation (IRQE = 1 in OPTION register).
EXT/INT = 1
INVSCLK = 0
RD = 0
CS
CNVST
BUSY
t3
t35
t36 t37
SCLK
1
t31
2
3
t32
14
15
16
SDOUT
t16
X D15
D14
D13
D1
D0
Figure 20. Slave Serial Data Timing for Reading (Read Previous Conversion during Conversion)
REV. B
BUSY
AD7676 NO. 2
(UPSTREAM)
BUSY
AD7676 NO. 1
(DOWNSTREAM)
BUSY
OUT
RDC/SDIN
SDOUT
CNVST
CS
SCLK
RDC/SDIN
SDOUT
CNVST
CS
SCLK
DATA
OUT
SCLK IN
CS IN
CNVST IN
Figure 21. Two AD7676s in a Daisy Chain Configuration
–17–
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