EVAL-AD7676CB View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-AD7676CB' PDF : 20 Pages View PDF
AD7676
SERIAL INTERFACE
The AD7676 is configured to use the serial interface when the
SER/PAR is held HIGH. The AD7676 outputs 16 bits of data
MSB first, on the SDOUT pin. This data is synchronized with
the 16 clock pulses provided on the SCLK pin.
MASTER SERIAL INTERFACE
Internal Clock
The AD7676 is configured to generate and provide the serial data
clock SCLK when the EXT/INT pin is held LOW. The AD7676 also
generates a SYNC signal to indicate to the host when the serial
data is valid. The serial clock SCLK and the SYNC signal can be
inverted if desired. The output data is valid on both the rising
and falling edges of the data clock. Depending on RDC/SDIN
input, the data can be read after each conversion or during the
following conversion. Figures 17 and 18 show the detailed timing
diagrams of these two modes.
Usually, because the AD7676 has a longer acquisition phase
than the conversion phase, the data is read immediately after
conversion. That makes the mode master, read after conversion,
the most recommended serial mode when it can be used.
CS, RD
EXT/INT = 0
t3
CNVST
RDC/SDIN = 0
INVSCLK = INVSYNC = 0
BUSY
SYNC
SCLK
SDOUT
t29
t14
t15
t16
t28
t18
t19
t20
t21
1
2
3
X
D15
D14
t22
t23
t30
t25
t24
t26
14
15
16
t27
D2
D1
D0
Figure 17. Master Serial Data Timing for Reading (Read after Conversion)
CS, RD
EXT/INT = 0
RDC/SDIN = 1
INVSCLK = INVSYNC = 0
CNVST
BUSY
t1
t3
SYNC
SCLK
t17
t14
t19
t20 t21
t15
1
t18
2
3
t25
t24
t26
14
15
16
t27
SDOUT
t16
X
t22
D15
D14
t23
D2
D1
D0
Figure 18. Master Serial Data Timing for Reading (Read Previous Conversion during Conversion)
REV. B
–15–
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