EVAL-AD7763EB View Datasheet(PDF) - Analog Devices

Part Name

Description

MFG CO.

EVAL-AD7763EB

24-Bit, 625 kSPS, 109 dB Σ-Δ ADC with On-Chip Buffers, Serial Interface

Analog Devices 

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AD7763

THEORY OF OPERATION

The AD7763 employs a Σ-Δ conversion technique to convert

the analog input into an equivalent digital word. The modulator

samples the input waveform and outputs an equivalent digital

word to the digital filter at a rate equal to ICLK.

Due to the high oversampling rate, which spreads the quanti-

zation noise from 0 to fICLK, the noise energy contained in the

band of interest is reduced (see Figure 23). To further reduce

quantization noise, a high order modulator is employed to shape

the noise spectrum; thus, most of the noise energy is shifted

out of the band of interest (see Figure 24).

The digital filtering that follows the modulator removes the

large out-of-band quantization noise (see Figure 25), while

also reducing the data rate from fICLK at the input of the filter

to fICLK/32 or less at the output of the filter, depending on the

decimation rate used.

Digital filtering has certain advantages over analog filtering.

It does not introduce significant noise or distortion and can

be made perfectly linear phase.

The AD7763 employs three finite impulse response (FIR) filters

in series. By using different combinations of decimation ratios

and filter selection, data can be obtained from the AD7763 at

four different data rates. The first filter receives data from the

modulator at ICLK MHz, where it is decimated × 4 to output

data at (ICLK/4) MHz.

Data Sheet

The second filter allows the decimation rate to be chosen from

8× to 32×. The third filter has a fixed decimation rate of 2×, is

user programmable, and has a default configuration (see the

Programmable FIR Filter section). This filter can be bypassed.

Table 6 shows some characteristics of the default filter. The group

delay of the filter is defined as the delay to the center of the

impulse response and is equal to the computation plus filter

delays. The delay until valid data is available (the DVALID status bit

is set) is equal to 2× the filter delay plus the computation delay.

QUANTIZATION NOISE

BAND OF INTEREST

fICLK/2

Figure 23. Σ-Δ ADC, Quantization Noise

NOISE SHAPING

BAND OF INTEREST

fICLK/2

Figure 24. Σ-Δ ADC, Noise Shaping

DIGITAL FILTER CUTOFF FREQUENCY

BAND OF INTEREST

fICLK/2

Figure 25. Σ-Δ ADC, Digital Filter Cutoff Frequency

Table 6. Configuration With Default Filter

ICLK

Frequency

Filter 1 Filter 2 Filter 3

20 MHz

4×

4×

2×

20 MHz

4×

8×

Bypassed

20 MHz

20 MHz

4×

8×

2×

4×

16×

Bypassed

20 MHz

20 MHz

4×

16×

2×

4×

32×

Bypassed

20 MHz

4×

12.288 MHz 4×

12.288 MHz 4×

12.288 MHz 4×

32×

2×

8×

2×

16×

2×

32×

Bypassed

12.288 MHz 4×

32×

2×

Data State

Fully filtered

Partially

filtered

Fully filtered

Partially

filtered

Fully filtered

Partially

filtered

Fully filtered

Fully filtered

Fully filtered

Partially

filtered

Fully filtered

Computation

Delay

1.775 μs

2.6 μs

2.25 μs

4.175 μs

3.1 μs

7.325 μs

4.65 μs

3.66 μs

5.05 μs

11.92 μs

7.57 μs

Filter

Delay

44.4 μs

10.8 μs

Pass Band

Bandwidth

250 kHz

140.625 kHz

87.6 μs

20.4 μs

125 kHz

70.3125 kHz

174 μs

39.6 μs

62.5 kHz

35.156 kHz

346.8 μs

142.6 μs

283.2 μs

64.45 μs

31.25 kHz

76.8 kHz

38.4 kHz

21.6 kHz

564.5 μs 19.2 kHz

Output Data Rate

(ODR)

625 kHz

625 kHz

312.5 kHz

312.5 kHz

156.25 kHz

156.25 kHz

78.125 kHz

192 kHz

96 kHz

96 kHz

48 kHz

Rev. B | Page 14 of 32

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