EVAL-AD7764EBZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
EVAL-AD7764EBZ
Analog Devices
'EVAL-AD7764EBZ' PDF : 32 Pages View PDF
AD7764
THEORY OF OPERATION
The AD7764 features an on-chip fully differential amplifier to
feed the Σ-Δ modulator pins , an on-chip reference buffer, and
a FIR filter block to perform the required digital filtering of the
Σ-Δ modulator output. Using this Σ-Δ conversion technique
with the added digital filtering, the analog input is converted to
an equivalent digital word.
Σ-Δ MODULATION AND DIGITAL FILTERING
The input waveform applied to the modulator is sampled and
an equivalent digital word is output to the digital filter at a rate
equal to ICLK. By employing oversampling, the quantization
noise is spread across a wide bandwidth from 0 to fICLK. This
means that the noise energy contained in the signal band of
interest is reduced (see Figure 29). To further reduce the
quantization noise, a high-order modulator is employed to
shape the noise spectrum so that most of the noise energy is
shifted out of the signal band (see Figure 30).
QUANTIZATION NOISE
BAND OF INTEREST
fICLK/2
Figure 29. Σ-Δ ADC, Quantization Noise
NOISE SHAPING
BAND OF INTEREST
fICLK/2
Figure 30. Σ-Δ ADC, Noise Shaping
The AD7764 employs three FIR filters in series. By using
different combinations of decimation ratios, data can be
obtained from the AD7764 at three data rates.
The first filter receives data from the modulator at ICLK MHz
where it is decimated 4× to output data at (ICLK/4) MHz. The
second filter allows the decimation rate to be chosen from
8× to 32×.
The digital filtering on the AD7764 provides full-band filtering.
This means that its stop-band attenuation occurs at the Nyquist
frequency (ODR/2). This feature provides increased protection
against aliasing of sampled frequencies that lie above the
Nyquist rate (ODR/2). The filter gives maximum attenuation at
the Nyquist rate (see Figure 32). This means that it attenuates all
possible alias frequencies by 110 dB. The frequency response in
Figure 32 occurs when the AD7764 is operated with a 40 MHz
MCLK in the decimate 64× mode. Note that the first stop-band
frequency occurs at Nyquist. The frequency response of the
filter scales with both the decimation rate chosen and the MCLK
frequency applied.
The third filter has a fixed decimation rate of 2×. Table 6 shows
some characteristics of the digital filtering where ICLK =
MCLK/2. The group delay of the filter is defined to be the delay
to the center of the impulse response and is equal to the compu-
tation plus the filter delays. The delay until valid data is available
(the FILTER-SETTLE status bit is set) is approximately twice
the filter delay plus the computation delay. This is listed in
terms of MCLK periods in Table 6.
0
PASS-BAND RIPPLE = 0.05dB
–0.1dB FREQUENCY = 125.1kHz
–3dB FREQUENCY = 128kHz
–20
STOP BAND = 156.25kHz
–40
–60
DIGITAL FILTER CUTOFF FREQUENCY
–80
BAND OF INTEREST
fICLK/2
–100
Figure 31. Σ-Δ ADC, Digital Filter Cutoff Frequency
–120
The digital filtering that follows the modulator removes the
large out-of-band quantization noise (see Figure 31) while also
reducing the data rate from fICLK at the input of the filter to
fICLK/64 or less at the output of the filter, depending on the
decimation rate used.
–140
–160
0
50
100
150
200
250
300
FREQUENCY (kHz)
Figure 32. Filter Frequency Response (312.5 kHz ODR)
Table 6. Configuration with Default Filter
ICLK
Frequency
Decimation
Rate
Data State
20 MHz
64×
Fully filtered
20 MHz
128×
Fully filtered
20 MHz
256×
Fully filtered
12.288 MHz
64×
Fully filtered
12.288 MHz
128×
Fully filtered
12.288 MHz
256×
Fully filtered
Computation
Delay
Filter Delay
2.25 μs
87.6 μs
3.1 μs
174 μs
4.65 μs
346.8 μs
3.66 μs
142.6 μs
5.05 μs
283.2 μs
7.57 μs
564.5 μs
Rev. 0 | Page 16 of 32
SYNC to
FILTER-SETTLE
7122 × tMCLK
14217 × tMCLK
27895 × tMCLK
7122 × tMCLK
14217 × tMCLK
27895 × tMCLK
Pass-Band
Bandwidth
125 kHz
62.5 kHz
31.25 kHz
76.8 kHz
38.4 kHz
19.2 kHz
Output Data Rate
(ODR)
312.5 kHz
156.25 kHz
78.125 kHz
192 kHz
96 kHz
48 kHz
Share Link: 