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EVAL-AD7764EBZ View Datasheet(PDF) - Analog Devices

Part Name
Description
MFG CO.
'EVAL-AD7764EBZ' PDF : 32 Pages View PDF
AD7764
AD7764 FUNCTIONALITY
SYNCHRONIZATION
The SYNC input to the AD7764 provides a synchronization
function that allows the user to begin gathering samples of the
analog front-end input from a known point in time.
The SYNC function allows multiple AD7764s, operated from
the same master clock, that use common SYNC and RESET
signals to be synchronized so that each ADC simultaneously
updates its output register.
Connect common MCLK, SYNC and RESET signals to all
AD7764 devices in the system. On the falling edge of the SYNC
signal, the digital filter sequencer is reset to 0. The filter is held
in a reset state until a rising edge of the SCO senses SYNC high.
Thus, to perform a synchronization of devices, a SYNC pulse of
a minimum of 2.5 ICLK cycles in length can be applied,
synchronous to the falling edge of SCO. On the first rising edge
of SCO after SYNC goes logic high, the filter is taken out of reset,
and the multiple parts gather input samples synchronously.
Following a SYNC, the digital filter needs time to settle before
valid data can be read from the AD7764. The user knows there
is valid data on the SDO line by checking the FILTER-SETTLE
status bit (see D7 in Table 9) that is output with each conversion
result. The time from the rising edge of SYNC until the FILTER-
SETTLE bit asserts depends on the filter configuration used. See
the Theory of Operation section and the values listed in Table 6
for details on calculating the time until FILTER-SETTLE
asserts. Note that the FILTER_SETTLE bit is designed as a
reactionary flag to indicate when the conversion data output
is valid.
OVERRANGE ALERTS
The AD7764 offers an overrange function in both a pin and
status bit output. The overrange alerts indicate when the voltage
applied to the AD7764 modulator input pins exceeds the limit
set in the overrange register, indicating that the voltage applied
is approaching a level where the modulator will be overranged.
To set this limit, the user must program the register. The default
overrange limit is set to 80% of the VREF voltage (see the
AD7764 Registers section).
The OVERRANGE pin outputs logic high to alert the user
that the modulator has sampled an input voltage greater in
magnitude than the overrange limit as set in the overrange
register. The OVERRANGE pin is set to logic high when the
modulator samples an input above the overrange limit. Once
the input returns below the limit, the OVERRANGE pin returns
to zero. The OVERRANGE pin is updated after the first FIR
filter stage. Its output changes at the ICLK/4 frequency.
The OVR status bit is output as Bit D6 on SDO during a data
conversion, and can be checked in the AD7764 status register.
This bit is less dynamic than the OVERRANGE pin output. It is
updated on each conversion result output, that is, the bit
changes at the output data rate. If the modulator has sampled a
voltage input that exceeded the overrange limit during the
process of gathering samples for a particular conversion result
output, then the OVR bit is set to logic high.
LOGIC
LEVEL
HI
LO
OUTPUT FREQUENCY
OF FIR FILTER 1 = ICLK/4
LOGIC
LEVEL
t
OVERRANGE
LIMIT
OBSOLUTE INPUT
TO AD7764
[(VIN+) – (VIN–)]
OUTPUT DATA RATE (ODR)
(ICLK/DECIMATION RATE
OVERRANGE
LIMIT
HI
LO
t
Figure 38. OVERRANGE Pin and OVR Bit vs. Absolute Voltage
Applied to Modulator
The output points from FIR Filter 1 in Figure 38 are not drawn
to scale relative to the output data rate points. The FIR Filter 1
output is updated either 16×, 32×, or 64× faster than the output
data rate depending on the decimation rate in operation.
POWER MODES
During power-up, the AD7764 defaults to operate in normal
power mode. There is no register write required.
The AD7764 also offers low power mode. To operate the device
in low power mode, the user sets the LPWR bit in the control
register to logic high (See Figure 39). Operating the AD7764 in
low power mode has no impact on the output data rate or
available bandwidth.
SCO (O)
32 × tSCO
FSI (I)
SDI (I)
CONTROL REGISTER
ADDRESS 0x0001
LOW POWER MODE
DATA 0x0010
Figure 39. Write Scheme for Low Power Mode
The AD7764 features a RESET/PWRDWN pin. Holding the
input to this pin logic low places the AD7764 in power-down
mode. All internal circuitry is reset. To utilize the RESET
functionality, pulse the input to this pin low for a minimum of
one MCLK period. This action resets the internal circuitry.
When the AD7764 receives a logic high input on the RESET/
PWRDWN pin, the device powers up.
Rev. 0 | Page 21 of 32
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