AD7764
AD7764 REGISTERS
The AD7764 has a number of user-programmable registers. The control register is used to set the functionality of the on-chip buffer and
differential amplifier and provides the option to power down the AD7764. There are also digital gain and overrange threshold registers.
Writing to these registers involves writing the register address followed by a 16-bit data word. The register addresses, details of individual
bits, and default values are provided in this section.
CONTROL REGISTER
Table 13. Control Register (Address 0x0001, Default Value 0x0000)
MSB
D15 D14 D13 D12 D11 D10 D9 D8 D7
0
RD
RD
0 RD
0 SYNC 0 BYPASS
OVR GAIN
STAT
REF
D6 D5 D4 D3
0 0 0 PWR
DOWN
LSB
D2 D1
D0
LPWR REF BUF AMP
OFF
OFF
Table 14. Bit Descriptions of Control Register
Bit Mnemonic Comment
14 RD OVR1, 2, Read Overrange. If this bit is set, the next read operation outputs the contents of the overrange threshold register
instead of a conversion result.
13 RD GAIN1, 2 Read Gain. If this bit is set, the next read operation outputs the contents of the digital gain register.
11 RD STAT1, 2 Read Status. If this bit is set, the next read operation outputs the contents of the status register.
9 SYNC1
Synchronize. Setting this bit initiates an internal synchronization routine. Setting this bit simultaneously on multiple
devices synchronizes all filters.
7 BYPASS REF Bypass Reference. Setting this bit bypasses the reference buffer if the buffer is off.
3 PWR DOWN Power Down. A logic high powers the device down without resetting. Writing a 0 to this bit powers the device back up.
2 LPWR
Low Power Mode. Set to Logic 1 when AD7764 is in low power mode.
1 REF BUF OFF Reference Buffer Off. Asserting this bit powers down the reference buffer.
0 AMP OFF Amplifier Off. Asserting this bit switches the differential amplifier off.
1 Bit 14 to Bit 11 and Bit 9 are self-clearing bits.
2 Only one of the bits can be set in any write operation because it determines the contents of the next read operation.
STATUS REGISTER
Table 15. Status Register (Read Only)
MSB
D15
D14 D13 D12 D11 D10
PARTNO 1 0 0 0 FILTER-
SETTLE
D9 D8 D7 D6 D5 D4
0
OVR 0 1 0 REF BUF
ON
D3
AMP
ON
D2
LPWR
D1
DEC 1
LSB
D0
DEC 0
Table 16. Bit Descriptions of Status Register
Bit
Mnemonic Comment
15
PARTNO Part Number. This bit is set to one for the AD7764.
10
FILTER-
Filter Settling Bit. This bit corresponds to the FILTER-SETTLE bit in the status word output in the second 16-bit read
SETTLE
operation. It indicates when data is valid.
9
0
Zero. This bit is set to Logic 0.
8
OVR
Overrange. If the current analog input exceeds the current overrange threshold, this bit is set.
4
REF BUF ON Reference Buffer On. This bit is set when the reference buffer is in use.
3
AMP ON Amplifier On. This bit is set when the input amplifier is in use.
2
LPWR
Low power mode. This bit is set when operating in low power mode.
1 to 0 DEC[1:0] Decimation Rate. These bits correspond to decimation rate in use.
Rev. 0 | Page 28 of 32