EVAL-AD7764EBZ View Datasheet(PDF) - Analog Devices

Part Name

Description

MFG CO.

EVAL-AD7764EBZ

24-Bit, 312 kSPS, 109 dB Σ-Δ ADC with On-Chip Buffers and Serial Interface

Analog Devices 

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AD7764

AD7764 INTERFACE

READING DATA

The AD7764 uses an SPI-compatible serial interface. The

timing diagram in Figure 2 shows how the AD7764 transmits its

conversion results.

The data read from the AD7764 is clocked out using the serial

clock output (SCO). The SCO frequency is half that of the

MCLK input to the AD7764.

The conversion result output on the serial data output (SDO)

line is framed by the frame synchronization output, FSO, which

is sent logic low for 32 SCO cycles. Each bit of the new

conversion result is clocked onto the SDO line on the rising

SCO edge and is valid on the falling SCO edge. The 32-bit result

consists of the 24 data bits followed by five status bits followed

further by three zeros. The five status bits are listed in Table 9

and described below the table.

Table 9. Status Bits During Data Read

D7

D6 D5

D4

FILTER-SETTLE OVR LPWR DEC_RATE 1

D3

DEC_RATE 0

• The FILTER-SETTLE bit indicates whether the data output

from the AD7764 is valid. After resetting the device (using

the RESET pin) or clearing the digital filter (using the

SYNC pin), the FILTER-SETTLE bit goes logic low to

indicate that the full settling time of the filter has not yet

passed and that the data is not yet valid. The FILTER-

SETTLE bit also goes to zero when the input to the part

has asserted the overrange alerts.

• The OVR (overrange) bit is described in the Overrange

Alerts section.

• The LPWR bit is set to logic high when the AD7764 is

operating in low power mode. See the Power Modes

section for further details.

• The DEC_RATE 1 and DEC_RATE 0 bits indicate the

decimation ratio used. Table 10 is a truth table for the

decimation rate bits.

Table 10. Decimation Rate Status Bits

Decimate

DEC_RATE 1

64×

0

1281×

1

256×

0

DEC_RATE 0

1

X

0

1Don’t care. If the DEC_RATE 1 bit is set to 1, AD7764 is in Decimate

128× mode.

READING STATUS AND OTHER REGISTERS

The AD7764 features a gain correction register, an overrange

register, and a read-only status register. To read back the

contents of these registers, the user must first write to the

control register of the device, and set the bit that corresponds to

the register to be read. The next read operation outputs the

contents of the selected register (on the SDO pin) instead of a

conversion result.

To ensure that the next read cycle contains the contents of the

register written to, the write operation to that register must be

completed a minimum of 8 × tSCO before the falling edge of FSO,

which indicates the start of the next read cycle. See Figure 4 for

further details.

The AD7764 Registers section provides more information on

the relevant bits in the control register.

WRITING TO THE AD7764

A write operation to the AD7764 is shown in Figure 3. The

serial writing operation is synchronous to the SCO signal. The

status of the frame synchronization input, FSI, is checked on the

falling edge of the SCO signal. If the FSI line is low, then the

first data bit on the serial data in (SDI) line is latched in on the

next SCO falling edge.

Set the active edge of the FSI signal to occur at a position when

the SCO signal is high or low to allow setup and hold times

from the SCO falling edge to be met. The width of the FSI

signal can be set to between 1 and 32 SCO periods wide. A

second, or subsequent, falling edge that occurs before

32 SCO periods have elapsed, is ignored.

Figure 3 details the format for the serial data being written to

the AD7764 through the SDI pin. Thirty-two bits are required

for a write operation. The first 16 bits are used to select the

register address that the data being read is intended for. The

second 16 bits contain the data for the selected register.

Writing to the AD7764 is allowed at any time, even while

reading a conversion result. Note that after writing to the

devices, valid data is not output until after the settling time for

the filter has elapsed. The FILTER-SETTLE status bit is asserted

at this point to indicate that the filter has settled and that valid

data is available at the output.

Rev. 0 | Page 20 of 32

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