EVAL-AD7934CB View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-AD7934CB' PDF : 32 Pages View PDF
AD7933/AD7934
Reading Data from the AD7933/AD7934
With the W/B pin tied logic high, the AD7933/AD7934
interface operates in word mode. In this case, a single read
operation from the device accesses the conversion data-word on
Pin DB0 to Pin DB11 (12-bit word) and Pin DB2 to DB11
(10-bit word). The DB8/HBEN pin assumes its DB8 function.
With the W/B pin tied to logic low, the AD7933/AD7934
interface operates in byte mode. In this case, the DB8/HBEN
pin assumes its HBEN function.
Conversion data from the AD7933/AD7934 must be accessed in
two read operations with eight bits of data provided on DB0 to
DB7 for each of the read operations. The HBEN pin determines
whether the read operation accesses the high byte or the low
byte of the 12- or 10-bit word. For a low byte read, DB0 to DB7
provide the eight LSBs of the 12-bit word. For 10-bit operation,
the two LSBs of the low byte are 0s and are followed by six bits
of conversion data. For a high byte read, DB0 to DB3 provide the
four MSBs of the 12-/10-bit word. DB4 and DB5 of the high byte
provide the Channel ID. DB6 and DB7 are always 0.
Figure 34 shows the read cycle timing diagram for a 12- or
10-bit transfer. When operating in word mode, the HBEN input
does not exist and only the first read operation is required to
access data from the device. When operating in byte mode, the
two read cycles shown in Figure 35 are required to access the
full data-word from the device.
The CS and RD signals are gated internally and the level is
triggered active low. In either word mode or byte mode, CS and
RD can be tied together as the timing specifications for t10 and
t11 are 0 ns minimum. This means the bus is constantly driven
by the AD7933/AD7934.
The data is placed onto the data bus a time t13 after both CS and
RD go low. The RD rising edge can be used to latch data out of
the device. After a time, t14, the data lines become three-stated.
Alternatively, CS and RD can be tied permanently low, and the
conversion data is valid and placed onto the data bus a time, t9,
before the falling edge of BUSY.
Note that if RD is pulsed during the conversion time, this
causes a degradation in linearity performance of approximately
0.25 LSB. Reading during conversion, by way of tying CS and
RD low, does not cause any degradation.
HBEN/DB8
CS
RD
DB0 TO DB7
t15
t16
t15
t10
t13
t11
t17
t12
t14
LOW BYTE
t16
HIGH BYTE
Figure 35. AD7933/AD7934 Parallel Interface—Read Cycle Timing for Byte Mode Operation (W/B = 0)
Rev. B | Page 24 of 32
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