EVAL-AD7934CB View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-AD7934CB' PDF : 32 Pages View PDF
POWER vs. THROUGHPUT RATE
A considerable advantage of powering the ADC down after a
conversion is that the power consumption of the part is
significantly reduced at lower throughput rates. When using the
different power modes, the AD7933/AD7934 are only powered
up for the duration of the conversion. Therefore, the average
power consumption per cycle is significantly reduced. Figure 39
shows a plot of power vs. throughput rate when operating in
autostandby mode for both VDD = 5 V and 3 V. For example, if
the device runs at a throughput rate of 10 kSPS, the overall cycle
time is 100 μs. If the maximum CLKIN frequency of 25.5 MHz
is used, the conversion time accounts for only 0.525 μs of the
overall cycle time while the AD7933/AD7934 remains in
standby mode for the remainder of the cycle.
Figure 40 shows a plot of the power vs. the throughput rate
when operating in normal mode for both VDD = 5 V and 3 V.
In both plots, the figures apply when using the internal
reference. If an external reference is used, the power-up time
reduces to 600 ns; therefore, the AD7933/AD7934 remains in
standby for a greater time in every cycle. Additionally, the
current consumption, when converting, should be lower than
the specified maximum of 2.7 mA with VDD = 5 V, or 2.0 mA
with VDD = 3 V, respectively.
1.8
TA = 25°C
1.6
1.4
VDD = 5V
1.2
1.0
0.8
0.6
VDD = 3V
0.4
0.2
0
0
20
40
60
80
100
120
140
THROUGHPUT (kSPS)
Figure 39. Power vs. Throughput in
Autostandby Mode Using Internal Reference
AD7933/AD7934
10
TA = 25°C
9
8
VDD = 5V
7
6
5
4
3
VDD = 3V
2
1
0
0 200 400 600 800 1000 1200 1400 1600
THROUGHPUT (kSPS)
Figure 40. Power vs. Throughput in Normal Mode Using Internal Reference
MICROPROCESSOR INTERFACING
AD7933/AD7934 to ADSP-21xx Interface
Figure 41 shows the AD7933/AD7934 interfaced to the
ADSP-21xx series of DSPs as a memory-mapped device.
A single wait state may be necessary to interface the AD7933/
AD7934 to the ADSP-21xx, depending on the clock speed of
the DSP. The wait state can be programmed via the data memory
wait state control register of the ADSP-21xx (see the ADSP-21xx
family User’s Manual for details). The following instruction
reads from the AD7933/AD7934:
MR = DM (ADC)
where ADC is the address of the AD7933/AD7934.
DSP/USER SYSTEM
A0 TO A15
ADSP-21xx*
DMS
IRQ2
WR
RD
ADDRESS BUS
ADDRESS
DECODER
CONVST
AD7933/
AD7934*
CS
BUSY
WR
RD
DB0 TO DB11
D0 TO D23
DATA BUS
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 41. Interfacing to the ADSP-21xx
Rev. B | Page 27 of 32
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