EVAL-AD7934CB View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-AD7934CB' PDF : 32 Pages View PDF
AD7933/AD7934
AD7933/AD7934 to ADSP-21065L Interface
Figure 42 shows a typical interface between the AD7933/AD7934
and the ADSP-21065L SHARC® processor. This interface is an
example of one of three DMA handshake modes. The MSX
control line is actually three memory select lines. Internal
ADDR25 to 24 are decoded into MS3 to 0, these lines are then
asserted as chip selects. The DMAR1 (DMA Request 1) is used
in this setup as the interrupt to signal the end of the conversion.
The rest of the interface is standard handshaking operation.
DSP/USER SYSTEM
ADDR0 TO ADDR23
ADDRESS BUS
CONVST
MSX
ADSP-21065L*
DMAR1
RD
WR
ADDRESS
LATCH
ADDRESS BUS
ADDRESS
DECODER
AD7933/
AD7934*
CS
BUSY
RD
WR
DB0 TO DB11
D0 TO D31
DATA BUS
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 42. Interfacing to the ADSP-21065L
AD7933/AD7934 to TMS32020, TMS320C25, and
TMS320C5x Interface
Parallel interfaces between the AD7933/AD7934 and the
TMS32020, TMS320C25 and TMS320C5x family of DSPs are
shown in Figure 43. Select the memory-mapped address for the
AD7933/AD7934 to fall in the I/O memory space of the DSPs.
The parallel interface on the AD7933/AD7934 is fast enough to
interface to the TMS32020 with no extra wait states. If high
speed glue logic, such as 74AS devices, is used to drive the
RD and the WR lines when interfacing to the TMS320C25, no
wait states are necessary. However, if slower logic is used, data
accesses may be slowed sufficiently when reading from, and
writing to, the part to require the insertion of one wait state.
Extra wait states are necessary when using the TMS320C5x at
their fastest clock speeds (see the TMS320C5x User’s Guide
for details).
Data is read from the ADC using the following instruction:
IN D, ADC
where:
D is the data memory address.
ADC is the AD7933/AD7934 address.
DSP/USER SYSTEM
A0 TO A15
TMS32020/
TMS320C25/
TMS320C50*
IS
ADDRESS BUS
EN
ADDRESS
DECODER
CONVST
AD7933/
AD7934*
CS
READY
MSC
STRB
R/W
TMS320C25
ONLY
WR
RD
INTX
DMD0 TO DMD15
DATA BUS
BUSY
DB11 TO DB0
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 43. Interfacing to TMS32020/TMS320C25/TMS320C5x
AD7933/AD7934 to 80C186 Interface
Figure 44 shows the AD7933/AD7934 interfaced to the 80C186
microprocessor. The 80C186 DMA controller provides two
independent, high speed DMA channels where data transfers
can occur between memory and I/O spaces. Each data transfer
consumes two bus cycles, one cycle to fetch data and the other
to store data. After the AD7933/AD7934 finish a conversion,
the BUSY line generates a DMA request to Channel 1 (DRQ1).
Because of the interrupt, the processor performs a DMA read
operation, which also resets the interrupt latch. Sufficient
priority must be assigned to the DMA channel to ensure that
the DMA request is serviced before the completion of the next
conversion.
MICROPROCESSOR/
USER SYSTEM
AD0 TO AD15 ADDRESS/DATA BUS
A16 TO A19
CONVST
ALE
80C186*
ADDRESS
LATCH
ADDRESS BUS
ADDRESS
DECODER
AD7933/
AD7934*
CS
DRQ1
QR
S
RD
WR
BUSY
RD
WR
DATA BUS DB0 TO DB11
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 44. Interfacing to the 80C186
Rev. B | Page 28 of 32
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