EVAL-AD7960FMCZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-AD7960FMCZ' PDF : 24 Pages View PDF
AD7960
POWER SUPPLY
The AD7960 uses both 5 V (VDD1) and 1.8 V (VDD2) power
supplies, as well as a digital input/output interface supply (VIO).
Drive the EN3 to EN0 pins with a 1.8 V logic level. VIO and
VDD2 can be taken from the same 1.8 V source; however, it is
best practice to isolate the VIO and VDD2 pins using separate
traces as well as to decouple each pin separately.
The 5 V and 1.8 V supplies required for the AD7960 can be
generated using Analog Devices, Inc., LDOs such as the
ADP7104-5 and the ADP124-1.8. Figure 33 shows the PSRR vs.
supply frequency of the AD7960. The AD7960 core power
scales with throughput as shown in Figure 34, offering
significant power budget savings at lower speed operation.
110
VDD2 = 1.8V
VIO = 1.8V
100
VDD1 = 5V
90
80
70
60
50
40
100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 33. PSRR vs. Supply Frequency
Data Sheet
Power-Up
As is best practice for all ADCs, power on the core supplies
prior to applying an external reference (where applicable).
Apply the analog inputs last.
When powering up the AD7960 device, first apply 1.8 V (VDD2,
VIO) to the device, then ramp 5 V (VDD1). Set the reference
configuration pins, EN0, EN1, and EN2, to the correct values.
When an internal reference buffer is used (governed by the EN1
and EN0 values), apply the external reference of 2.048 V to the
REFIN pin or 5 V/4.096 V to the REF pin.
45
40
35
30
25
20
15
10
5
0
0
1
2
3
4
5
THROUGHPUT (MHz)
Figure 34. ADC Core Power Dissipation vs. Throughput, Self Clocked Mode,
CNV± in CMOS Mode, Internal Reference Buffer Disabled
Rev. C | Page 18 of 24
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